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PLY-based parsers.
Verilog Python
tree: f90f9a3704

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Examples
Syntax
.gitignore
README.org
full_parser.py
liberty.py
netlist.py
ply_boolean_expressions.py
ply_liberty.py
ply_verilog_netlist.py
sublime-project

README.org

Parser for Gate Project

This project contains ply-based parsers for Liberty gate libraries and Verilog netlists. Note that these are not tested. They may only work for a subset of general grammars.

Dependencies

Python Lex-Yacc by dabeaz

Todo

  • gate functions should take input, output, and current_state vectors
  • ablity to print stats for gates/library
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