32-bit RISC-V system on chip for iCE40 FPGAs
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boards Add commented flash_* pins to blackice-ii.pcf Apr 2, 2018
.gitignore Add BlackIce-II support Mar 18, 2018
.gitlab-ci.yml Add yosys-config --datdir workaround Dec 15, 2017
LICENSE Add README and LICENSE Jan 4, 2018
Makefile Replace up5k define with the new boards/*-defines.sv mechanism Mar 18, 2018
README.md Add note about the required version of Icarus to the README Apr 2, 2018
bus_arbiter.sv Combine the instruction and data buses Dec 25, 2017
clk_div.sv Fix compatibility with iverilog Dec 9, 2017
progmem.c Add mtime and mtimecmp addresses to progmem.c Jan 23, 2018
progmem.lds Add rodata to the linker script Dec 25, 2017
ram.sv Swap byte order in the ram module Dec 26, 2017
rv32.sv Add memory-mapped mtime and mtimecmp registers Jan 23, 2018
rv32_alu.sv Move result zero/non-zero test to the execute stage Dec 30, 2017
rv32_branch.sv Move result zero/non-zero test to the execute stage Dec 30, 2017
rv32_control.sv Move CSR access to the execute stage Dec 30, 2017
rv32_csrs.sv Add memory-mapped mtime and mtimecmp registers Jan 23, 2018
rv32_decode.sv Add missing csr_src connection from the control unit to the flip flop Dec 30, 2017
rv32_execute.sv Add memory-mapped mtime and mtimecmp registers Jan 23, 2018
rv32_fetch.sv Add static branch prediction Dec 30, 2017
rv32_hazard.sv Add static branch prediction Dec 30, 2017
rv32_imm.sv Split decode stage into smaller modules Dec 27, 2017
rv32_mem.sv Move result zero/non-zero test to the execute stage Dec 30, 2017
rv32_opcodes.sv Add static branch prediction Dec 30, 2017
rv32_regs.sv Explicitly instantiate all registers to 0 Dec 31, 2017
start.s Replace x0 with zero Jan 5, 2018
sync.sv Fix compatibility with iverilog Dec 9, 2017
timer.sv Add memory-mapped mtime and mtimecmp registers Jan 23, 2018
top.sv Replace up5k define with the new boards/*-defines.sv mechanism Mar 18, 2018
top.ys Replace up5k define with the new boards/*-defines.sv mechanism Mar 18, 2018
uart.sv Merge memory bus inputs/outputs in the port list Dec 12, 2017

README.md

Icicle

Introduction

Icicle is a 32-bit RISC-V system on chip for iCE40 HX8K and iCE40 UP5K FPGAs. It can be built with the open-source Project IceStorm toolchain and currently targets several development boards.

Current features

  • RV32I core with a classic 5-stage RISC pipeline, static branch prediction, bypassing and interlocking. It currently implements the entire user ISA (except ECALL and EBREAK) and parts of the privileged ISA.
  • Shared instruction and data memory (8 KiB, implemented with FPGA block RAM).
  • Memory-mapped UART and LEDs.

Dependencies

Building and testing

Supported boards

Icicle supports several development boards:

<board> should be replaced with the internal name of your development board in the rest of the instructions (e.g. ice40hx8k-b-evn for the iCE40-HX8K breakout board).

Building

  • Run make BOARD=<board> syntax to check the syntax with Icarus, which has a stricter parser than Yosys. At the time of writing the master branch of Icarus is required as there isn't a stable release with always_comb/always_ff support yet.
  • Run make BOARD=<board> to synthesize the design, place and route, compile the demo program in progmem.c and create the bitstream.

Programming

iCE40-HX8K breakout board

  • Configure the jumpers for direct SRAM programming.
  • Run make BOARD=ice40hx8k-b-evn flash to flash the bitstream.

BlackIce II

  • Configure jumper on board for DFU Mode and connect both USB1 and USB2 on the board to host USB ports.
  • Run make BOARD=blackice-ii dfu-flash to flash the bitstream.

Testing

  • If your chosen board has built-in LEDs, some of the LEDs should turn on.
  • Run picocom -b 9600 /dev/ttyUSBn (replacing ttyUSBn with the name of the serial port) to connect to the serial port. Hello, world! should be printed once per second.

Other targets

The make BOARD=<board> stat target runs icebox_stat and the make BOARD=<board> time target prints the icetime report.

The Makefile runs the IceStorm toolchain in quiet mode. Unset the QUIET variable to run the toolchain in verbose mode - e.g. make BOARD=<board> QUIET= ....

Planned features

  • Use remaining block RAM tiles to eke out as much memory as possible.
  • Use the SPRAM tiles on UP5K devices.
  • Implement remaining bits of the user ISA.
  • Implement machine mode from the privileged ISA.
  • Interrupts/exceptions.
  • Unaligned memory access support.
  • Memory-mapped GPIOs.
  • Memory-mapped XIP/SPI flash.
  • Improved reset support (a reset signal + boot ROM to zero all the registers).
  • Automated tests.
  • Multiply/divide support.
  • Compressed instruction support.
  • Add flags to disable certain features (e.g. privileged mode) to save LUTs on smaller devices (e.g. the UP5K).
  • Investigate using DSP tiles on the UP5K.

Size and performance

The entire system on chip currently occupies around 2,500 LUTs on an iCE40 when synthesized with Yosys.

It's currently clocked at 24 MHz but icetime estimates it could be clocked at ~30-35 MHz (depending on how lucky arachne-pnr is).

The core is capable of issuing and retiring one instruction per clock cycle, although the actual number of instructions per cycle will be slightly less than this in practice due to interlocking, branch mispredictions and the shared memory bus.

License

This project is available under the terms of the ISC license, which is similar to the 2-clause BSD license. See the LICENSE file for the copyright information and licensing terms.