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README.md

Icicle

Introduction

Icicle is a 32-bit RISC-V system on chip for iCE40 HX8K, iCE40 UP5K and ECP5 FPGAs. It can be built with the open-source SymbiFlow toolchain and currently targets several development boards.

Current features

  • RV32I core with a classic 5-stage RISC pipeline, static branch prediction, bypassing and interlocking. It currently implements the entire user ISA parts of the privileged ISA.
  • Shared instruction and data memory (8 KiB, implemented with FPGA block RAM).
  • Memory-mapped UART and LEDs.
  • Memory-mapped SPI flash.

Dependencies

Building and testing

Supported boards

Icicle supports several development boards:

<board> should be replaced with the internal name of your development board in the rest of the instructions (e.g. ice40hx8k-b-evn for the iCE40-HX8K breakout board).

Building

  • Run make BOARD=<board> syntax to check the syntax with Icarus, which has a stricter parser than Yosys. At the time of writing the master branch of Icarus is required as there isn't a stable release with always_comb/always_ff support yet.
  • Run make BOARD=<board> to synthesize the design, place and route, compile the demo program in progmem.c and create the bitstream.

Programming

BlackIce II

  • Configure jumper on board for DFU Mode and connect both USB1 and USB2 on the board to host USB ports.
  • Run make BOARD=blackice-ii dfu-flash to flash the bitstream.

ECP5 evaluation board

  • Remove R22, R23 and R24 to disconnect the channel B of the FTDI chip from the I2C bus.
  • Populate R34 and R35 with zero-ohm resistors to connect channel B of the FTDI chip to the UART RX and TX pins.
  • Optionally populate R21 with a zero-ohm resistor to enable the UART TX indicator LED.

iCE40-HX8K breakout board

  • Configure the jumpers for flash programming.
  • Run make BOARD=ice40hx8k-b-evn flash to flash the bitstream.

Testing

  • If your chosen board has built-in LEDs, some of the LEDs should turn on.
  • Run picocom -b 9600 /dev/ttyUSBn (replacing ttyUSBn with the name of the serial port) to connect to the serial port. Hello, world! should be printed once per second.

Other targets

The make BOARD=<board> stat target runs icebox_stat and the make BOARD=<board> time target prints the icetime report.

The Makefile runs the IceStorm toolchain in quiet mode. Unset the QUIET variable to run the toolchain in verbose mode - e.g. make BOARD=<board> QUIET= ....

Set the PNR variable to arachne-pnr to use arachne-pnr instead of nextpnr (the default) - e.g. make PNR=arachne-pnr.

Formal verification

Icicle supports the RISC-V Formal Interface (RVFI), allowing it to be formally verified with SymbiYosys and riscv-formal:

  • Run git clone https://github.com/SymbioticEDA/riscv-formal to clone riscv-formal.
  • Run cd riscv-formal/cores && git clone https://github.com/grahamedgecombe/icicle to clone Icicle in the cores subdirectory.
  • Run ``cd icicle && python ../../checks/genchecks.py && make -C checks -j `nproc``` to verify the core.

Planned features

  • Use remaining block RAM tiles to eke out as much memory as possible.
  • Use the SPRAM tiles on UP5K devices.
  • Implement remaining bits of the user ISA.
  • Implement machine mode from the privileged ISA.
  • Interrupts/exceptions.
  • Unaligned memory access support.
  • Memory-mapped GPIOs.
  • Add XIP, DDR, DSPI and QSPI support to the SPI flash controller.
  • Improved reset support (a reset signal + boot ROM to zero all the registers).
  • Automated tests.
  • Multiply/divide support.
  • Compressed instruction support.
  • Add flags to disable certain features (e.g. privileged mode) to save LUTs on smaller devices (e.g. the UP5K).
  • Investigate using DSP tiles on the UP5K.

Size and performance

The entire system on chip currently occupies around 3,000 LUTs on an iCE40 when synthesized with Yosys.

If bypassing and branch prediction are disabled nextpnr estimates it can be clocked at around 50 MHz on a HX series device and 20 MHz on a UP series device.

The core is capable of issuing and retiring one instruction per clock cycle, although the actual number of instructions per cycle will be slightly less than this in practice due to interlocking, branch mispredictions and the shared memory bus.

License

This project is available under the terms of the ISC license, which is similar to the 2-clause BSD license. See the LICENSE file for the copyright information and licensing terms.

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