- RV32I core with a classic 5-stage RISC pipeline, static branch
prediction, bypassing and interlocking. It currently implements the entire
user ISA (except
EBREAK) and parts of the privileged ISA.
- Shared instruction and data memory (8 KiB, implemented with FPGA block RAM).
- Memory-mapped UART and LEDs.
- GNU RISC-V toolchain
- GNU Make
- Icarus Verilog (
- Project IceStorm
- vim (for
Building and testing
Icicle supports several development boards:
<board> should be replaced with the internal name of your development board in
the rest of the instructions (e.g.
ice40hx8k-b-evn for the iCE40-HX8K breakout
make BOARD=<board> syntaxto check the syntax with Icarus, which has a stricter parser than Yosys. At the time of writing the
masterbranch of Icarus is required as there isn't a stable release with
make BOARD=<board>to synthesize the design, place and route, compile the demo program in
progmem.cand create the bitstream.
iCE40-HX8K breakout board
- Configure the jumpers for direct SRAM programming.
make BOARD=ice40hx8k-b-evn flashto flash the bitstream.
- Configure jumper on board for DFU Mode and connect both USB1 and USB2 on the board to host USB ports.
make BOARD=blackice-ii dfu-flashto flash the bitstream.
- If your chosen board has built-in LEDs, some of the LEDs should turn on.
picocom -b 9600 /dev/ttyUSBn(replacing
ttyUSBnwith the name of the serial port) to connect to the serial port.
Hello, world!should be printed once per second.
make BOARD=<board> stat target runs
icebox_stat and the
make BOARD=<board> time target prints the
Makefile runs the IceStorm toolchain in quiet mode. Unset the
QUIET variable to run the toolchain in verbose mode - e.g.
make BOARD=<board> QUIET= ....
- Use remaining block RAM tiles to eke out as much memory as possible.
- Use the SPRAM tiles on UP5K devices.
- Implement remaining bits of the user ISA.
- Implement machine mode from the privileged ISA.
- Unaligned memory access support.
- Memory-mapped GPIOs.
- Memory-mapped XIP/SPI flash.
- Improved reset support (a reset signal + boot ROM to zero all the registers).
- Automated tests.
- Multiply/divide support.
- Compressed instruction support.
- Add flags to disable certain features (e.g. privileged mode) to save LUTs on smaller devices (e.g. the UP5K).
- Investigate using DSP tiles on the UP5K.
Size and performance
The entire system on chip currently occupies around 2,500 LUTs on an iCE40 when synthesized with Yosys.
It's currently clocked at 24 MHz but
icetime estimates it could be clocked at
~30-35 MHz (depending on how lucky arachne-pnr is).
The core is capable of issuing and retiring one instruction per clock cycle, although the actual number of instructions per cycle will be slightly less than this in practice due to interlocking, branch mispredictions and the shared memory bus.
This project is available under the terms of the ISC license, which is similar
to the 2-clause BSD license. See the
LICENSE file for the copyright
information and licensing terms.