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Reset all FFs
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tomverbeure committed May 21, 2018
1 parent e87ce65 commit 4c73c21
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Showing 9 changed files with 84 additions and 0 deletions.
2 changes: 2 additions & 0 deletions clk_div.sv
Expand Up @@ -9,6 +9,8 @@ module clk_div #(
);
logic [LOG_DIVISOR-1:0] q;

initial q = 0;

always_ff @(posedge clk_in)
q <= q + 1;

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5 changes: 5 additions & 0 deletions rv32.sv
Expand Up @@ -9,6 +9,7 @@

module rv32 (
input clk,
input reset_,

/* instruction memory bus */
output logic [31:0] instr_address_out,
Expand Down Expand Up @@ -160,6 +161,7 @@ module rv32 (

rv32_fetch fetch (
.clk(clk),
.reset_(reset_),

/* control in (from hazard) */
.stall_in(fetch_stall),
Expand Down Expand Up @@ -190,6 +192,7 @@ module rv32 (

rv32_decode decode (
.clk(clk),
.reset_(reset_),

/* control in (from hazard) */
.stall_in(decode_stall),
Expand Down Expand Up @@ -249,6 +252,7 @@ module rv32 (

rv32_execute execute (
.clk(clk),
.reset_(reset_),

/* control in (from hazard) */
.stall_in(execute_stall),
Expand Down Expand Up @@ -316,6 +320,7 @@ module rv32 (

rv32_mem mem (
.clk(clk),
.reset_(reset_),

/* control in (from hazard) */
.stall_in(mem_stall),
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6 changes: 6 additions & 0 deletions rv32_csrs.sv
Expand Up @@ -144,6 +144,7 @@

module rv32_csrs (
input clk,
input reset_,
input stall_in,

/* control in */
Expand Down Expand Up @@ -346,6 +347,11 @@ module rv32_csrs (

cycle <= cycle + 1;
instret <= instret + instr_retired_in;

if (!reset_) begin
cycle <= 0;
instret <= 0;
end
end
endmodule

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29 changes: 29 additions & 0 deletions rv32_decode.sv
Expand Up @@ -6,6 +6,7 @@

module rv32_decode (
input clk,
input reset_,

/* control in (from hazard) */
input stall_in,
Expand Down Expand Up @@ -202,6 +203,34 @@ module rv32_decode (
rd_write_out <= 0;
end
end

if (!reset_) begin
branch_predicted_taken_out <= 0;
valid_out <= 0;
rs1_out <= 0;
rs2_out <= 0;
alu_op_out <= 0;
alu_sub_sra_out <= 0;
alu_src1_out <= 0;
alu_src2_out <= 0;
mem_read_out <= 0;
mem_write_out <= 0;
mem_width_out <= 0;
mem_zero_extend_out <= 0;
mem_fence_out <= 0;
csr_read_out <= 0;
csr_write_out <= 0;
csr_write_op_out <= 0;
csr_src_out <= 0;
branch_op_out <= 0;
branch_pc_src_out <= 0;
rd_out <= 0;
rd_write_out <= 0;

pc_out <= 0;
imm_value_out <= 0;
csr_out <= 0;
end
end
endmodule

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19 changes: 19 additions & 0 deletions rv32_execute.sv
Expand Up @@ -7,6 +7,7 @@

module rv32_execute (
input clk,
input reset_,

/* control in (from hazard) */
input stall_in,
Expand Down Expand Up @@ -121,6 +122,7 @@ module rv32_execute (

rv32_csrs csrs (
.clk(clk),
.reset_(reset_),
.stall_in(stall_in),

/* control in */
Expand Down Expand Up @@ -189,6 +191,23 @@ module rv32_execute (
rd_write_out <= 0;
end
end

if (!reset_) begin
branch_predicted_taken_out <= 0;
valid_out <= 0;
alu_non_zero_out <= 0;
mem_read_out <= 0;
mem_write_out <= 0;
mem_width_out <= 0;
mem_zero_extend_out <= 0;
mem_fence_out <= 0;
branch_op_out <= 0;
rd_out <= 0;
rd_write_out <= 0;
rs2_value_out <= 0;
branch_pc_out <= 0;
result_out <= 0;
end
end
endmodule

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8 changes: 8 additions & 0 deletions rv32_fetch.sv
Expand Up @@ -5,6 +5,7 @@

module rv32_fetch (
input clk,
input reset_,

/* control in (from hazard) */
input stall_in,
Expand Down Expand Up @@ -79,6 +80,13 @@ module rv32_fetch (
if (flush_in)
instr_out <= `RV32_INSTR_NOP;
end

if (!reset_) begin
branch_predicted_taken_out <= 0;
instr_out <= 0;
next_pc <= 0;
pc_out <= 0;
end
end
endmodule

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8 changes: 8 additions & 0 deletions rv32_mem.sv
Expand Up @@ -9,6 +9,7 @@

module rv32_mem (
input clk,
input reset_,

/* control in (from hazard) */
input stall_in,
Expand Down Expand Up @@ -168,6 +169,13 @@ module rv32_mem (
rd_write_out <= 0;
end
end

if (!reset_) begin
valid_out <= 0;
rd_out <= 0;
rd_write_out <= 0;
rd_value_out <= 0;
end
end
endmodule

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5 changes: 5 additions & 0 deletions timer.sv
Expand Up @@ -8,6 +8,7 @@

module timer (
input clk,
input reset_,

/* cycle count (from the CPU core) */
input [63:0] cycle_in,
Expand Down Expand Up @@ -66,6 +67,10 @@ module timer (
end
endcase
end

if (!reset_) begin
mtimecmp <= 0;
end
end
endmodule

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2 changes: 2 additions & 0 deletions top.sv
Expand Up @@ -132,6 +132,7 @@ module top (

rv32 rv32 (
.clk(pll_clk),
.reset_(!reset),

/* instruction memory bus */
.instr_address_out(instr_address),
Expand Down Expand Up @@ -216,6 +217,7 @@ module top (

timer timer (
.clk(pll_clk),
.reset_(!reset),

/* cycle count (from the CPU core) */
.cycle_in(cycle),
Expand Down

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