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JTAGulator: Assisted discovery of on-chip debug interfaces
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.travis.yml Update .travis.yml Apr 24, 2017
CHANGES.markdown Updated for FW version 1.6, added .EEPROM file Aug 9, 2018
JDCogSerial.spin Lot o' more stuff! Jul 30, 2014
JTAGulator.eeprom Updated for FW version 1.6, added .EEPROM file Aug 9, 2018
JTAGulator.spin Updated for FW version 1.6, added .EEPROM file Aug 9, 2018
JTAGulatorCon.spin Update copyright dates Mar 9, 2018
JTAGulatorUtil.spin Add Set_Pins_Low method to set all pins low within a specified channe… Jun 29, 2018
PropJTAG.spin Clarified some comments Jul 2, 2018
PropSerial.spin Increased buffer size to maximum (256 bytes) Mar 9, 2018
README.markdown Fixed another link typo Dec 25, 2015
RealRandom.spin Initial commit: 1.0 (DESIGN West, April 24, 2013) May 4, 2013
TODO.markdown No more UART feature creep Mar 9, 2018
jm_rxserial.spin
jm_txserial.spin Changed from sending 2 stops bits to 1 stop bit (for consistency) Mar 9, 2018

README.markdown

JTAGulator

A tool to assist in identifying on-chip debugging (OCD) and/or programming connections from test points, vias, or component pads on a target piece of hardware.

Refer to the project page for complete details:

http://www.jtagulator.com

Direct link to video demonstrating the firmware update process:

http://www.youtube.com/watch?v=xlXwy-weG1M

Author

Created by Joe Grand of Grand Idea Studio.

License

The JTAGulator design is distributed under a Creative Commons Attribution 3.0 United States license. This means that you can share and adapt the work, but you must attribute the work to the original author.

The JTAGulator name and logo are registered trademarks of Grand Idea Studio. No permission is granted to use the marks without our express consent.

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