A tool to assist in identifying on-chip debugging (OCD) and/or programming connections from test points, vias, or component pads on a target piece of hardware.
Refer to the project page for more details:
Created by Joe Grand of Grand Idea Studio.
The JTAGulator design is distributed under a Creative Commons Attribution 3.0 United States license. This means that you can share and adapt the work, but you must attribute the work to the original author.
The JTAGulator name and logo are registered trademarks of Grand Idea Studio. No permission is granted to use the marks without our express consent.