A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.
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mips32r1
LEGAL
README

README

MIPS32-R1
---------

This is an implementation of the MIPS32 Release 1 processor.


At a Glance
-----------

- Bare-metal (no MMU; direct physical addressing).
- No caches: Instead, an extremely generic 4-way memory handshake.
- No FPU. Software floating point is supported.
- Just about as small as you can get for pipelined MIPS32r1.


Architecture
------------

- Single-issue in-order 5-stage pipeline with full forwarding and hazard
  detection.
- Harvard architecture with separate instruction and data ports.
- All required MIPS32 instructions are implemented, including hardware
  multiplication and integer division, fused multiply/add, atomic
  load-linked and store conditional, and unaligned loads and stores.
- Complete Coprocessor 0 allows ISA-compliant interrupts, exceptions,
  and user/kernel modes.
- No MMU. This is a bare-metal processor.
- No FPU, with toolchain support for software-based floating point.
- Hardware divider is small, multicycle, and runs asynchronously from the
  pipeline thus allowing some masking of latency in certain scenarios.
- Memory interface is separate from the processor for flexibility with
  connecting various RAMs. It utilizes a general-purpose four-way handshake.
- Hardware is big- or little-endian and supports reversible endian
  in User mode.
- Parameterized addresses for exception/interrupt vectors and boundary
  address between user/kernel regions.
- Extensive documentation in-source and elsewhere.
- Vendor-independent code.
- A clean, modular design written from scratch.


Design Notes
------------

The files in this directory create a complete MIPS32 processor. The top-level
module is "Processor.v". Its interface includes 5 general-purpose hardware
interrupts, a non-maskable hardware interrupt, the 8 pending ISA interrupts
(for diagnostics--this can be removed), and a memory interface for both
instructions and data.

The memory interface is implemented as a four-way handshake:

    1. Read/Write request goes high.
    2. Ack goes high when data is available.
    3. Read/Write request goes low.
    4. Ack signal goes low.
            ____
    R/W: __|    |____
               ____
    Ack: _____|    |____

This interface is simple and robust but will limit the performance of the
system. For example, because the instruction memory fetches only once per
handshake, the minimum theoretical CPI is greatly increased from 1 to
between 3 and 4.

If you want to achieve maximum performance (IPC close to 1.0), you must
modify the memory handshake! (One future goal of this project is to provide
a simple i-cache and single-cycle instruction accesses to the front-end.)


History
-------

This design was created by Grant Ayers and was originally funded by the
eXtensible Utah Multicore (XUM, "zoom") project at the University of Utah
from 2010-2012. The name "XUM" appears in various design documents and
is a notable distinguisher between this family of MIPS implementations and
other extant designs. The project was previously hosted on OpenCores
as 'mips32r1'. A snapshot of the XUM project can be found at
https://github.com/grantea/mips32r1_xum. It includes a Virtex-5 SoC,
many hardware drivers, software demos, and gcc-based toolchain instructions.
However, further development of the processor will occur in this repository.


Legal
-----

All software and hardware included in this distribution is licensed under
the GNU LGPL. See the file 'LEGAL' in the project root directory for
more information.


Feel free to send questions or feedback to ayers AT cs DOT stanford.edu.