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Popular repositories

  1. Misc things related to the Raspberry Pi Pico / RP2040

    C 7

  2. A collection of tools and libraries for working with V3D on the Raspberry Pi

    C 1

  3. Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

    SystemVerilog

  4. Forked from embench/embench-iot

    The main Embench repository

    C

  5. Forked from google/riscv-dv

    SV/UVM based instruction generator for RISC-V processor verification

    SystemVerilog

592 contributions in the last year

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Contribution activity

June 2021

Created a pull request in lowRISC/ibex that received 3 comments

Testing producing junit XML

Modifications to sim.py will still need some work, this is primarily to test the integration with azure JUnit reporting.

+289 −89 3 comments

Created an issue in lowRISC/opentitan that received 2 comments

[topgen] Adding an OTP clock connection to OTBN

I'm having trouble adding an OTP clock connection to OTBN, I altered top_earlgrey.hjson to add the connection: { name: "otbn", type: "otbn", clock…

2 comments

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