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ddrdrive: add some defines and structures

these are taken from the example and documentation.

Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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1 parent f61a1a9 commit 18b13bb0ec09f0d4dfb62ebf4e820ad2d3ef03cc @gregkh committed Jun 25, 2009
Showing with 80 additions and 0 deletions.
  1. +80 −0 ddrdrive.c
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80 ddrdrive.c
@@ -12,6 +12,86 @@
#include <linux/module.h>
#include <linux/pci.h>
+#define PATHID 0x0
+#define TARGETID 0x0
+#define LUN 0x0
+
+#define SECTOR_SIZE 0x00000200
+#define SECTOR_SIZE_BIG_ENDIAN 0x00020000
+
+#define SGL_HOST_ADDRESS_REG 0x00
+#define SGL_CARD_READ_REG 0x04
+#define SGL_CARD_WRITE_REG 0x08
+#define INT_STATUS_REG 0x0C
+#define EXT_LED_CONTROL_REG 0x20
+#define INT_CONTROL_REG 0x130
+#define AC_ADAPTER_REG 0x134
+#define LED_YELLOW_CONTROL 0x158
+#define LED_RED_CONTROL 0x15C
+#define BACKUP_RESTORE_CONTROL 0x210
+#define BACKUP_RESTORE_ADDRESS 0x214
+#define BACKUP_RESTORE_STATUS 0x218
+#define NAND0_ECC_ERROR_TOTAL 0x23C
+#define NAND1_ECC_ERROR_TOTAL 0x24C
+
+#define LED_TURN_ON 0xC0000000
+#define LED_TURN_OFF 0xA0000000
+
+#define SCSIOP_DDRDRIVE_UNIQUE 0xFF
+#define SUBCODE_READ_REGISTER 0x02
+#define SUBCODE_WRITE_REGISTER 0x03
+#define SUBCODE_BRICK_STATE 0x04
+#define SUBCODE_DRIVER_VERSION 0x07
+#define SUBCODE_FPGA_REVISION 0x0C
+#define SUBCODE_DRIVE_BACKUP 0x11
+#define SUBCODE_DRIVE_RESTORE 0x12
+
+#define ANY_INTERRUPT_MASK 0x5500003F
+#define BRICK_PWR_ON_MASK 0x40000000
+#define BRICK_PWR_OFF_MASK 0x10000000
+#define BACKUP_COMPLETE_MASK 0x04000000
+#define RESTORE_COMPLETE_MASK 0x01000000
+#define SGL_COMPLETION_MASK 0x0000003F
+
+#define MAX_SGL_QUEUE 0x20 /* 32 SGL's */
+#define SGL_SIZE 0x600 /* 16 Byte Aligned */
+#define MAX_DMA_SIZE 0x10000 /* 64KB */
+#define MAX_DMA_TRANSFERS 0x80000000 /* 256 DMA's */
+#define PHYSICAL_BREAKS 0xFF /* 255 */
+#define UNCACHED_EXT_SIZE 0xC000 /* MAX_SGL_QUEUE * SGL_SIZE */
+#define MAX_TRANSFER_SIZE 0xFF000 /* PHYSICAL_BREAKS * 0x1000 */
+
+/*
+ * DMA Group Data Structure - See DDRdrive DMA Engine V8.0 Specification
+ */
+struct dma_group {
+ u16 byte_count1;
+ u16 byte_count2;
+ u32 host_addr1;
+ u32 host_addr2;
+};
+
+/*
+ * DDRdrive X1 Device Extension
+ */
+struct ddr_ext {
+ u8 *bar0;
+ u8 *virt_sg_list;
+ u32 phys_sg_list;
+ u32 queue_head;
+ u32 queue_tail;
+ u32 queue_count;
+/*
+ PSCSI_REQUEST_BLOCK pSrbQueue[MAX_SGL_QUEUE];
+ PSCSI_REQUEST_BLOCK pSrbBackup;
+ PSCSI_REQUEST_BLOCK pSrbRestore;
+*/
+ u32 hba_state;
+ u32 brick_state;
+ u32 last_sector;
+};
+
+
static struct pci_device_id ids[] = {
{ PCI_DEVICE(0x19e3, 0xdd52) },
{ },

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