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0c4490c @gregkh initial 4.40 import
authored
1 /**
2 * \file ati_pcigart.c
3 * ATI PCI GART support
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8 /*
9 * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
10 *
11 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
12 * All Rights Reserved.
13 *
14 * Permission is hereby granted, free of charge, to any person obtaining a
15 * copy of this software and associated documentation files (the "Software"),
16 * to deal in the Software without restriction, including without limitation
17 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
18 * and/or sell copies of the Software, and to permit persons to whom the
19 * Software is furnished to do so, subject to the following conditions:
20 *
21 * The above copyright notice and this permission notice (including the next
22 * paragraph) shall be included in all copies or substantial portions of the
23 * Software.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
26 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
27 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
28 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
29 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
30 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
31 * DEALINGS IN THE SOFTWARE.
32 */
33
34 #include "drmP.h"
35
36 # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
37
38 static __inline__ void insert_page_into_table(struct drm_ati_pcigart_info *info, u32 page_base, u32 *pci_gart)
39 {
40 switch(info->gart_reg_if) {
41 case DRM_ATI_GART_IGP:
42 *pci_gart = cpu_to_le32((page_base) | 0xc);
43 break;
44 case DRM_ATI_GART_PCIE:
45 *pci_gart = cpu_to_le32((page_base >> 8) | 0xc);
46 break;
47 default:
48 case DRM_ATI_GART_PCI:
49 *pci_gart = cpu_to_le32(page_base);
50 break;
51 }
52 }
53
54 static __inline__ u32 get_page_base_from_table(struct drm_ati_pcigart_info *info, u32 *pci_gart)
55 {
56 u32 retval;
57 switch(info->gart_reg_if) {
58 case DRM_ATI_GART_IGP:
59 retval = *pci_gart;
60 retval &= ~0xc;
61 break;
62 case DRM_ATI_GART_PCIE:
63 retval = *pci_gart;
64 retval &= ~0xc;
65 retval <<= 8;
66 break;
67 default:
68 case DRM_ATI_GART_PCI:
69 retval = *pci_gart;
70 break;
71 }
72 return retval;
73 }
74
75
76
77 static void *drm_ati_alloc_pcigart_table(int order)
78 {
79 unsigned long address;
80 struct page *page;
81 int i;
82
83 DRM_DEBUG("%s: alloc %d order\n", __FUNCTION__, order);
84
85 address = __get_free_pages(GFP_KERNEL | __GFP_COMP,
86 order);
87 if (address == 0UL) {
88 return NULL;
89 }
90
91 page = virt_to_page(address);
92
93 for (i = 0; i < order; i++, page++) {
94 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15)
95 get_page(page);
96 #endif
97 SetPageReserved(page);
98 }
99
100 DRM_DEBUG("%s: returning 0x%08lx\n", __FUNCTION__, address);
101 return (void *)address;
102 }
103
104 static void drm_ati_free_pcigart_table(void *address, int order)
105 {
106 struct page *page;
107 int i;
108 int num_pages = 1 << order;
109 DRM_DEBUG("%s\n", __FUNCTION__);
110
111 page = virt_to_page((unsigned long)address);
112
113 for (i = 0; i < num_pages; i++, page++) {
114 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15)
115 __put_page(page);
116 #endif
117 ClearPageReserved(page);
118 }
119
120 free_pages((unsigned long)address, order);
121 }
122
123 int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
124 {
125 struct drm_sg_mem *entry = dev->sg;
126 unsigned long pages;
127 int i;
128 int order;
129 int num_pages, max_pages;
130
131 /* we need to support large memory configurations */
132 if (!entry) {
133 DRM_ERROR("no scatter/gather memory!\n");
134 return 0;
135 }
136
137 order = drm_order((gart_info->table_size + (PAGE_SIZE-1)) / PAGE_SIZE);
138 num_pages = 1 << order;
139
140 if (gart_info->bus_addr) {
141 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
142 pci_unmap_single(dev->pdev, gart_info->bus_addr,
143 num_pages * PAGE_SIZE,
144 PCI_DMA_TODEVICE);
145 }
146
147 max_pages = (gart_info->table_size / sizeof(u32));
148 pages = (entry->pages <= max_pages)
149 ? entry->pages : max_pages;
150
151 for (i = 0; i < pages; i++) {
152 if (!entry->busaddr[i])
153 break;
154 pci_unmap_single(dev->pdev, entry->busaddr[i],
155 PAGE_SIZE, PCI_DMA_TODEVICE);
156 }
157
158 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
159 gart_info->bus_addr = 0;
160 }
161
162
163 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN
164 && gart_info->addr) {
165
166 drm_ati_free_pcigart_table(gart_info->addr, order);
167 gart_info->addr = NULL;
168 }
169
170 return 1;
171 }
172 EXPORT_SYMBOL(drm_ati_pcigart_cleanup);
173
174 int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
175 {
176 struct drm_sg_mem *entry = dev->sg;
177 void *address = NULL;
178 unsigned long pages;
179 u32 *pci_gart, page_base, bus_address = 0;
180 int i, j, ret = 0;
181 int order;
182 int max_pages;
183 int num_pages;
184
185 if (!entry) {
186 DRM_ERROR("no scatter/gather memory!\n");
187 goto done;
188 }
189
190 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
191 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
192
193 order = drm_order((gart_info->table_size +
194 (PAGE_SIZE-1)) / PAGE_SIZE);
195 num_pages = 1 << order;
196 address = drm_ati_alloc_pcigart_table(order);
197 if (!address) {
198 DRM_ERROR("cannot allocate PCI GART page!\n");
199 goto done;
200 }
201
202 if (!dev->pdev) {
203 DRM_ERROR("PCI device unknown!\n");
204 goto done;
205 }
206
207 bus_address = pci_map_single(dev->pdev, address,
208 num_pages * PAGE_SIZE,
209 PCI_DMA_TODEVICE);
210 if (bus_address == 0) {
211 DRM_ERROR("unable to map PCIGART pages!\n");
212 order = drm_order((gart_info->table_size +
213 (PAGE_SIZE-1)) / PAGE_SIZE);
214 drm_ati_free_pcigart_table(address, order);
215 address = NULL;
216 goto done;
217 }
218 } else {
219 address = gart_info->addr;
220 bus_address = gart_info->bus_addr;
221 DRM_DEBUG("PCI: Gart Table: VRAM %08X mapped at %08lX\n",
222 bus_address, (unsigned long)address);
223 }
224
225 pci_gart = (u32 *) address;
226
227 max_pages = (gart_info->table_size / sizeof(u32));
228 pages = (entry->pages <= max_pages)
229 ? entry->pages : max_pages;
230
231 memset(pci_gart, 0, max_pages * sizeof(u32));
232
233 for (i = 0; i < pages; i++) {
234 /* we need to support large memory configurations */
235 entry->busaddr[i] = pci_map_single(dev->pdev,
236 page_address(entry->
237 pagelist[i]),
238 PAGE_SIZE, PCI_DMA_TODEVICE);
239 if (entry->busaddr[i] == 0) {
240 DRM_ERROR("unable to map PCIGART pages!\n");
241 drm_ati_pcigart_cleanup(dev, gart_info);
242 address = NULL;
243 bus_address = 0;
244 goto done;
245 }
246 page_base = (u32) entry->busaddr[i];
247
248 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
249 insert_page_into_table(gart_info, page_base, pci_gart);
250 pci_gart++;
251 page_base += ATI_PCIGART_PAGE_SIZE;
252 }
253 }
254
255 ret = 1;
256
257 #if defined(__i386__) || defined(__x86_64__)
258 wbinvd();
259 #else
260 mb();
261 #endif
262
263 done:
264 gart_info->addr = address;
265 gart_info->bus_addr = bus_address;
266 return ret;
267 }
268 EXPORT_SYMBOL(drm_ati_pcigart_init);
269
270 static int ati_pcigart_needs_unbind_cache_adjust(struct drm_ttm_backend *backend)
271 {
272 return ((backend->flags & DRM_BE_FLAG_BOUND_CACHED) ? 0 : 1);
273 }
274
275 static int ati_pcigart_populate(struct drm_ttm_backend *backend,
276 unsigned long num_pages,
277 struct page **pages)
278 {
279 ati_pcigart_ttm_backend_t *atipci_be =
280 container_of(backend, ati_pcigart_ttm_backend_t, backend);
281
282 DRM_ERROR("%ld\n", num_pages);
283 atipci_be->pages = pages;
284 atipci_be->num_pages = num_pages;
285 atipci_be->populated = 1;
286 return 0;
287 }
288
289 static int ati_pcigart_bind_ttm(struct drm_ttm_backend *backend,
290 struct drm_bo_mem_reg *bo_mem)
291 {
292 ati_pcigart_ttm_backend_t *atipci_be =
293 container_of(backend, ati_pcigart_ttm_backend_t, backend);
294 off_t j;
295 int i;
296 struct drm_ati_pcigart_info *info = atipci_be->gart_info;
297 u32 *pci_gart;
298 u32 page_base;
299 unsigned long offset = bo_mem->mm_node->start;
300 pci_gart = info->addr;
301
302 DRM_ERROR("Offset is %08lX\n", bo_mem->mm_node->start);
303 j = offset;
304 while (j < (offset + atipci_be->num_pages)) {
305 if (get_page_base_from_table(info, pci_gart+j))
306 return -EBUSY;
307 j++;
308 }
309
310 for (i = 0, j = offset; i < atipci_be->num_pages; i++, j++) {
311 struct page *cur_page = atipci_be->pages[i];
312 /* write value */
313 page_base = page_to_phys(cur_page);
314 insert_page_into_table(info, page_base, pci_gart + j);
315 }
316
317 #if defined(__i386__) || defined(__x86_64__)
318 wbinvd();
319 #else
320 mb();
321 #endif
322
323 atipci_be->gart_flush_fn(atipci_be->dev);
324
325 atipci_be->bound = 1;
326 atipci_be->offset = offset;
327 /* need to traverse table and add entries */
328 DRM_DEBUG("\n");
329 return 0;
330 }
331
332 static int ati_pcigart_unbind_ttm(struct drm_ttm_backend *backend)
333 {
334 ati_pcigart_ttm_backend_t *atipci_be =
335 container_of(backend, ati_pcigart_ttm_backend_t, backend);
336 struct drm_ati_pcigart_info *info = atipci_be->gart_info;
337 unsigned long offset = atipci_be->offset;
338 int i;
339 off_t j;
340 u32 *pci_gart = info->addr;
341
342 DRM_DEBUG("\n");
343
344 if (atipci_be->bound != 1)
345 return -EINVAL;
346
347 for (i = 0, j = offset; i < atipci_be->num_pages; i++, j++) {
348 *(pci_gart + j) = 0;
349 }
350 atipci_be->gart_flush_fn(atipci_be->dev);
351 atipci_be->bound = 0;
352 atipci_be->offset = 0;
353 return 0;
354 }
355
356 static void ati_pcigart_clear_ttm(struct drm_ttm_backend *backend)
357 {
358 ati_pcigart_ttm_backend_t *atipci_be =
359 container_of(backend, ati_pcigart_ttm_backend_t, backend);
360
361 DRM_DEBUG("\n");
362 if (atipci_be->pages) {
363 backend->func->unbind(backend);
364 atipci_be->pages = NULL;
365
366 }
367 atipci_be->num_pages = 0;
368 }
369
370 static void ati_pcigart_destroy_ttm(struct drm_ttm_backend *backend)
371 {
372 ati_pcigart_ttm_backend_t *atipci_be;
373 if (backend) {
374 DRM_DEBUG("\n");
375 atipci_be = container_of(backend, ati_pcigart_ttm_backend_t, backend);
376 if (atipci_be) {
377 if (atipci_be->pages) {
378 backend->func->clear(backend);
379 }
380 drm_ctl_free(atipci_be, sizeof(*atipci_be), DRM_MEM_TTM);
381 }
382 }
383 }
384
385 static struct drm_ttm_backend_func ati_pcigart_ttm_backend =
386 {
387 .needs_ub_cache_adjust = ati_pcigart_needs_unbind_cache_adjust,
388 .populate = ati_pcigart_populate,
389 .clear = ati_pcigart_clear_ttm,
390 .bind = ati_pcigart_bind_ttm,
391 .unbind = ati_pcigart_unbind_ttm,
392 .destroy = ati_pcigart_destroy_ttm,
393 };
394
395 struct drm_ttm_backend *ati_pcigart_init_ttm(struct drm_device *dev, struct drm_ati_pcigart_info *info, void (*gart_flush_fn)(struct drm_device *dev))
396 {
397 ati_pcigart_ttm_backend_t *atipci_be;
398
399 atipci_be = drm_ctl_calloc(1, sizeof (*atipci_be), DRM_MEM_TTM);
400 if (!atipci_be)
401 return NULL;
402
403 atipci_be->populated = 0;
404 atipci_be->backend.func = &ati_pcigart_ttm_backend;
405 atipci_be->gart_info = info;
406 atipci_be->gart_flush_fn = gart_flush_fn;
407 atipci_be->dev = dev;
408
409 return &atipci_be->backend;
410 }
411 EXPORT_SYMBOL(ati_pcigart_init_ttm);
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