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1 LIBRARY ieee;
2 use ieee.std_logic_1164.all;
3 USE IEEE.numeric_std.ALL;
4 USE IEEE.std_logic_UNSIGNED.ALL;
5 use IEEE.std_logic_arith.all;
6
7 library work;
8 use work.trb_net_std.all;
9 use work.trb_net_components.all;
10 use work.trb_net16_hub_func.all;
11
12 use work.trb_net_gbe_components.all;
13 use work.trb_net_gbe_protocols.all;
14
15 entity CNTester_module is
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16 generic ( g_GENERATE_STAT : integer range 0 to 1 := 0);
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17 port (
18 CLKSYS_IN : in std_logic;
19 CLKGBE_IN : in std_logic;
20 RESET : in std_logic;
21 GSR_N : in std_logic;
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22 LINK_OK_OUT : out std_logic;
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23
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24 MAC_ADDR_IN : in std_logic_vector(47 downto 0);
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25 TIMESTAMP_IN : in std_logic_vector(31 downto 0);
26 DEST_ADDR_IN : in std_logic_vector(15 downto 0);
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27 GENERATE_PACKET_IN : in std_logic;
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28 SIZE_IN : in std_logic_vector(15 downto 0);
29 BUSY_OUT : out std_logic;
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30
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31 MODULE_SELECT_OUT : out std_logic_vector(7 downto 0);
32 MODULE_RD_EN_OUT : out std_logic;
33 MODULE_DATA_IN : in std_logic_vector(71 downto 0);
34 STOP_TRANSMISSION_OUT : out std_logic;
35 START_STAT_IN : in std_logic;
36
37 MODULE_DATA_OUT : out std_logic_vector(71 downto 0);
38 MODULE_RD_EN_IN : in std_logic;
39 MODULE_SELECTED_IN : in std_logic;
40 MODULE_FULL_OUT : out std_logic;
41
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42 TEST_PORT_IN : in std_logic_vector(123 downto 0);
43 TEST_PORT_OUT : out std_logic_vector(123 downto 0);
44
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45 CNTRL_PACKET_SIZE_OUT : out std_logic_vector(15 downto 0);
46
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47 -- serdes io
48 SD_RX_CLK_IN : in std_logic;
49 SD_TX_DATA_OUT : out std_logic_vector(7 downto 0);
50 SD_TX_KCNTL_OUT : out std_logic;
51 SD_TX_CORRECT_DISP_OUT : out std_logic;
52 SD_RX_DATA_IN : in std_logic_vector(7 downto 0);
53 SD_RX_KCNTL_IN : in std_logic;
54 SD_RX_DISP_ERROR_IN : in std_logic;
55 SD_RX_CV_ERROR_IN : in std_logic;
56 SD_RX_SERDES_RST_OUT : out std_logic;
57 SD_RX_PCS_RST_OUT : out std_logic;
58 SD_TX_PCS_RST_OUT : out std_logic;
59 SD_RX_LOS_IN : in std_logic;
60 SD_SIGNAL_DETECTED_IN : in std_logic;
61 SD_RX_CDR_IN : in std_logic;
62 SD_TX_PLL_LOL_IN : in std_logic;
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63 SD_QUAD_RST_OUT : out std_logic;
64 SD_XMIT_OUT : out std_logic
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65 );
66 end entity CNTester_module;
67
68 architecture CNTester_module of CNTester_module is
69
70
71 component tsmac34
72 port(
73 --------------- clock and reset port declarations ------------------
74 hclk : in std_logic;
75 txmac_clk : in std_logic;
76 rxmac_clk : in std_logic;
77 reset_n : in std_logic;
78 txmac_clk_en : in std_logic;
79 rxmac_clk_en : in std_logic;
80 ------------------- Input signals to the GMII ----------------
81 rxd : in std_logic_vector(7 downto 0);
82 rx_dv : in std_logic;
83 rx_er : in std_logic;
84 col : in std_logic;
85 crs : in std_logic;
86 -------------------- Input signals to the CPU I/F -------------------
87 haddr : in std_logic_vector(7 downto 0);
88 hdatain : in std_logic_vector(7 downto 0);
89 hcs_n : in std_logic;
90 hwrite_n : in std_logic;
91 hread_n : in std_logic;
92 ---------------- Input signals to the Tx MAC FIFO I/F ---------------
93 tx_fifodata : in std_logic_vector(7 downto 0);
94 tx_fifoavail : in std_logic;
95 tx_fifoeof : in std_logic;
96 tx_fifoempty : in std_logic;
97 tx_sndpaustim : in std_logic_vector(15 downto 0);
98 tx_sndpausreq : in std_logic;
99 tx_fifoctrl : in std_logic;
100 ---------------- Input signals to the Rx MAC FIFO I/F ---------------
101 rx_fifo_full : in std_logic;
102 ignore_pkt : in std_logic;
103 -------------------- Output signals from the GMII -----------------------
104 txd : out std_logic_vector(7 downto 0);
105 tx_en : out std_logic;
106 tx_er : out std_logic;
107 -------------------- Output signals from the CPU I/F -------------------
108 hdataout : out std_logic_vector(7 downto 0);
109 hdataout_en_n : out std_logic;
110 hready_n : out std_logic;
111 cpu_if_gbit_en : out std_logic;
112 ---------------- Output signals from the Tx MAC FIFO I/F ---------------
113 tx_macread : out std_logic;
114 tx_discfrm : out std_logic;
115 tx_staten : out std_logic;
116 tx_done : out std_logic;
117 tx_statvec : out std_logic_vector(30 downto 0);
118 ---------------- Output signals from the Rx MAC FIFO I/F ---------------
119 rx_fifo_error : out std_logic;
120 rx_stat_vector : out std_logic_vector(31 downto 0);
121 rx_dbout : out std_logic_vector(7 downto 0);
122 rx_write : out std_logic;
123 rx_stat_en : out std_logic;
124 rx_eof : out std_logic;
125 rx_error : out std_logic
126 );
127 end component;
128
129 --*********
130 -- MOST OF THE SIGNAL ARE NOT NEEDED, JUST COPIED FROM THE ORIGINAL BUF
131
132 signal pc_wr_en : std_logic;
133 signal pc_data : std_logic_vector(7 downto 0);
134 signal pc_eod : std_logic;
135 signal pc_sos : std_logic;
136 signal pc_ready : std_logic;
137 signal pc_padding : std_logic;
138 signal pc_decoding : std_logic_vector(31 downto 0);
139 signal pc_event_id : std_logic_vector(31 downto 0);
140 signal pc_queue_dec : std_logic_vector(31 downto 0);
141 signal pc_max_frame_size : std_logic_vector(15 downto 0);
142 signal pc_bsm_constr : std_logic_vector(3 downto 0);
143 signal pc_bsm_load : std_logic_vector(3 downto 0);
144 signal pc_bsm_save : std_logic_vector(3 downto 0);
145 signal pc_shf_empty : std_logic;
146 signal pc_shf_full : std_logic;
147 signal pc_shf_wr_en : std_logic;
148 signal pc_shf_rd_en : std_logic;
149 signal pc_shf_q : std_logic_vector(7 downto 0);
150 signal pc_df_empty : std_logic;
151 signal pc_df_full : std_logic;
152 signal pc_df_wr_en : std_logic;
153 signal pc_df_rd_en : std_logic;
154 signal pc_df_q : std_logic_vector(7 downto 0);
155 signal pc_all_ctr : std_logic_vector(4 downto 0);
156 signal pc_sub_ctr : std_logic_vector(4 downto 0);
157 signal pc_bytes_loaded : std_logic_vector(15 downto 0);
158 signal pc_size_left : std_logic_vector(31 downto 0);
159 signal pc_sub_size_to_save : std_logic_vector(31 downto 0);
160 signal pc_sub_size_loaded : std_logic_vector(31 downto 0);
161 signal pc_sub_bytes_loaded : std_logic_vector(31 downto 0);
162 signal pc_queue_size : std_logic_vector(31 downto 0);
163 signal pc_act_queue_size : std_logic_vector(31 downto 0);
164
165 signal fee_read : std_logic;
166 signal cts_readout_finished : std_logic;
167 signal cts_dataready : std_logic;
168 signal cts_length : std_logic_vector(15 downto 0);
169 signal cts_data : std_logic_vector(31 downto 0); -- DHDR of rest packet
170 signal cts_error_pattern : std_logic_vector(31 downto 0);
171
172 signal pc_sub_size : std_logic_vector(31 downto 0);
173 signal pc_trig_nr : std_logic_vector(31 downto 0);
174
175 signal tc_wr_en : std_logic;
176 signal tc_data : std_logic_vector(7 downto 0);
177 signal tc_ip_size : std_logic_vector(15 downto 0);
178 signal tc_udp_size : std_logic_vector(15 downto 0);
179 signal tc_ident : std_logic_vector(15 downto 0);
180 signal tc_flags_offset : std_logic_vector(15 downto 0);
181 signal tc_sod : std_logic;
182 signal tc_eod : std_logic;
183 signal tc_h_ready : std_logic;
184 signal tc_ready : std_logic;
185 signal fc_dest_mac : std_logic_vector(47 downto 0);
186 signal fc_dest_ip : std_logic_vector(31 downto 0);
187 signal fc_dest_udp : std_logic_vector(15 downto 0);
188 signal fc_src_mac : std_logic_vector(47 downto 0);
189 signal fc_src_ip : std_logic_vector(31 downto 0);
190 signal fc_src_udp : std_logic_vector(15 downto 0);
191 signal fc_type : std_logic_vector(15 downto 0);
192 signal fc_ihl_version : std_logic_vector(7 downto 0);
193 signal fc_tos : std_logic_vector(7 downto 0);
194 signal fc_ttl : std_logic_vector(7 downto 0);
195 signal fc_protocol : std_logic_vector(7 downto 0);
196 signal fc_bsm_constr : std_logic_vector(7 downto 0);
197 signal fc_bsm_trans : std_logic_vector(3 downto 0);
198
199 signal ft_data : std_logic_vector(8 downto 0);-- gk 04.05.10
200 signal ft_tx_empty : std_logic;
201 signal ft_start_of_packet : std_logic;
202 signal ft_bsm_init : std_logic_vector(3 downto 0);
203 signal ft_bsm_mac : std_logic_vector(3 downto 0);
204 signal ft_bsm_trans : std_logic_vector(3 downto 0);
205
206 signal mac_haddr : std_logic_vector(7 downto 0);
207 signal mac_hdataout : std_logic_vector(7 downto 0);
208 signal mac_hcs : std_logic;
209 signal mac_hwrite : std_logic;
210 signal mac_hread : std_logic;
211 signal mac_fifoavail : std_logic;
212 signal mac_fifoempty : std_logic;
213 signal mac_fifoeof : std_logic;
214 signal mac_hready : std_logic;
215 signal mac_hdata_en : std_logic;
216 signal mac_tx_done : std_logic;
217 signal mac_tx_read : std_logic;
218
219 signal serdes_clk_125 : std_logic;
220 signal mac_tx_clk_en : std_logic;
221 signal mac_rx_clk_en : std_logic;
222 signal mac_col : std_logic;
223 signal mac_crs : std_logic;
224 signal pcs_txd : std_logic_vector(7 downto 0);
225 signal pcs_tx_en : std_logic;
226 signal pcs_tx_er : std_logic;
227 signal pcs_an_lp_ability : std_logic_vector(15 downto 0);
228 signal pcs_an_complete : std_logic;
229 signal pcs_an_page_rx : std_logic;
230
231 signal pcs_stat_debug : std_logic_vector(63 downto 0);
232
233 signal stage_stat_regs : std_logic_vector(31 downto 0);
234 signal stage_ctrl_regs : std_logic_vector(31 downto 0);
235
236 signal analyzer_debug : std_logic_vector(63 downto 0);
237
238 signal ip_cfg_start : std_logic;
239 signal ip_cfg_bank : std_logic_vector(3 downto 0);
240 signal ip_cfg_done : std_logic;
241
242 signal ip_cfg_mem_addr : std_logic_vector(7 downto 0);
243 signal ip_cfg_mem_data : std_logic_vector(31 downto 0);
244 signal ip_cfg_mem_clk : std_logic;
245
246 -- gk 22.04.10
247 signal max_packet : std_logic_vector(31 downto 0);
248 signal min_packet : std_logic_vector(31 downto 0);
249 signal use_gbe : std_logic;
250 signal use_trbnet : std_logic;
251 signal use_multievents : std_logic;
252 -- gk 26.04.10
253 signal readout_ctr : std_logic_vector(23 downto 0);
254 signal readout_ctr_valid : std_logic;
255 signal gbe_trig_nr : std_logic_vector(31 downto 0);
256 -- gk 28.04.10
257 signal pc_delay : std_logic_vector(31 downto 0);
258 -- gk 04.05.10
259 signal ft_eod : std_logic;
260 -- gk 08.06.10
261 signal mac_tx_staten : std_logic;
262 signal mac_tx_statevec : std_logic_vector(30 downto 0);
263 signal mac_tx_discfrm : std_logic;
264
265 -- gk 21.07.10
266 signal allow_large : std_logic;
267
268 -- gk 28.07.10
269 signal bytes_sent_ctr : std_logic_vector(31 downto 0);
270 signal monitor_sent : std_logic_vector(31 downto 0);
271 signal monitor_dropped : std_logic_vector(31 downto 0);
272 signal monitor_sm : std_logic_vector(31 downto 0);
273 signal monitor_lr : std_logic_vector(31 downto 0);
274 signal monitor_hr : std_logic_vector(31 downto 0);
275 signal monitor_fifos : std_logic_vector(31 downto 0);
276 signal monitor_fifos_q : std_logic_vector(31 downto 0);
277 signal monitor_discfrm : std_logic_vector(31 downto 0);
278
279 -- gk 02.08.10
280 signal discfrm_ctr : std_logic_vector(31 downto 0);
281
282 -- gk 30.09.10
283 signal fc_rd_en : std_logic;
284 signal link_ok : std_logic;
285 signal link_ok_timeout_ctr : std_logic_vector(15 downto 0);
286
287 type linkStates is (ACTIVE, INACTIVE, TIMEOUT, FINALIZE);
288 signal link_current_state, link_next_state : linkStates;
289
290 signal link_down_ctr : std_logic_vector(15 downto 0);
291 signal link_down_ctr_lock : std_logic;
292
293 signal link_state : std_logic_vector(3 downto 0);
294
295 signal monitor_empty : std_logic_vector(31 downto 0);
296
297 -- gk 07.10.10
298 signal pc_eos : std_logic;
299
300 -- gk 09.12.10
301 signal frame_delay : std_logic_vector(31 downto 0);
302
303 -- gk 13.02.11
304 signal pcs_rxd : std_logic_vector(7 downto 0);
305 signal pcs_rx_en : std_logic;
306 signal pcs_rx_er : std_logic;
307 signal mac_rx_eof : std_logic;
308 signal mac_rx_er : std_logic;
309 signal mac_rxd : std_logic_vector(7 downto 0);
310 signal mac_rx_fifo_err : std_logic;
311 signal mac_rx_fifo_full : std_logic;
312 signal mac_rx_en : std_logic;
313 signal mac_rx_stat_en : std_logic;
314 signal mac_rx_stat_vec : std_logic_vector(31 downto 0);
315 signal fr_q : std_logic_vector(8 downto 0);
316 signal fr_rd_en : std_logic;
317 signal fr_frame_valid : std_logic;
318 signal rc_rd_en : std_logic;
319 signal rc_q : std_logic_vector(8 downto 0);
320 signal rc_frames_rec_ctr : std_logic_vector(31 downto 0);
321 signal tc_pc_ready : std_logic;
322 signal tc_pc_h_ready : std_logic;
323 signal mc_ctrl_frame_req : std_logic;
324 signal mc_data : std_logic_vector(8 downto 0);
325 signal mc_rd_en : std_logic;
326 signal fc_wr_en : std_logic;
327 signal fc_data : std_logic_vector(7 downto 0);
328 signal fc_ip_size : std_logic_vector(15 downto 0);
329 signal fc_udp_size : std_logic_vector(15 downto 0);
330 signal fc_ident : std_logic_vector(15 downto 0);
331 signal fc_flags_offset : std_logic_vector(15 downto 0);
332 signal fc_sod : std_logic;
333 signal fc_eod : std_logic;
334 signal fc_h_ready : std_logic;
335 signal fc_ready : std_logic;
336 signal rc_frame_ready : std_logic;
337 signal allow_rx : std_logic;
338 signal fr_frame_size : std_logic_vector(15 downto 0);
339 signal rc_frame_size : std_logic_vector(15 downto 0);
340 signal mc_frame_size : std_logic_vector(15 downto 0);
341 signal ic_dest_mac : std_logic_vector(47 downto 0);
342 signal ic_dest_ip : std_logic_vector(31 downto 0);
343 signal ic_dest_udp : std_logic_vector(15 downto 0);
344 signal ic_src_mac : std_logic_vector(47 downto 0);
345 signal ic_src_ip : std_logic_vector(31 downto 0);
346 signal ic_src_udp : std_logic_vector(15 downto 0);
347 signal pc_transmit_on : std_logic;
348 signal rc_bytes_rec : std_logic_vector(31 downto 0);
349 signal rc_debug : std_logic_vector(63 downto 0);
350 signal mc_busy : std_logic;
351 signal tsmac_gbit_en : std_logic;
352 signal mc_transmit_ctrl : std_logic;
353 signal mc_transmit_data : std_logic;
354 signal rc_loading_done : std_logic;
355 signal fr_get_frame : std_logic;
356 signal mc_transmit_done : std_logic;
357
358 signal dbg_fr : std_logic_vector(95 downto 0);
359 signal dbg_rc : std_logic_vector(63 downto 0);
360 signal dbg_mc : std_logic_vector(63 downto 0);
361 signal dbg_tc : std_logic_vector(63 downto 0);
362
363 signal fr_allowed_types : std_logic_vector(31 downto 0);
364 signal fr_allowed_ip : std_logic_vector(31 downto 0);
365 signal fr_allowed_udp : std_logic_vector(31 downto 0);
366
367 signal fr_frame_proto : std_logic_vector(15 downto 0);
368 signal rc_frame_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
369
370 signal dbg_select_rec : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
371 signal dbg_select_sent : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
372 signal dbg_select_protos : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
373
374 signal serdes_rx_clk : std_logic;
375
376 signal vlan_id : std_logic_vector(31 downto 0);
377 signal mc_type : std_logic_vector(15 downto 0);
378 signal fr_src_mac : std_logic_vector(47 downto 0);
379 signal fr_dest_mac : std_logic_vector(47 downto 0);
380 signal fr_src_ip : std_logic_vector(31 downto 0);
381 signal fr_dest_ip : std_logic_vector(31 downto 0);
382 signal fr_src_udp : std_logic_vector(15 downto 0);
383 signal fr_dest_udp : std_logic_vector(15 downto 0);
384 signal rc_src_mac : std_logic_vector(47 downto 0);
385 signal rc_dest_mac : std_logic_vector(47 downto 0);
386 signal rc_src_ip : std_logic_vector(31 downto 0);
387 signal rc_dest_ip : std_logic_vector(31 downto 0);
388 signal rc_src_udp : std_logic_vector(15 downto 0);
389 signal rc_dest_udp : std_logic_vector(15 downto 0);
390
391 signal mc_dest_mac : std_logic_vector(47 downto 0);
392 signal mc_dest_ip : std_logic_vector(31 downto 0);
393 signal mc_dest_udp : std_logic_vector(15 downto 0);
394 signal mc_src_mac : std_logic_vector(47 downto 0);
395 signal mc_src_ip : std_logic_vector(31 downto 0);
396 signal mc_src_udp : std_logic_vector(15 downto 0);
397
398 signal dbg_ft : std_logic_vector(63 downto 0);
399
400 signal fr_ip_proto : std_logic_vector(7 downto 0);
401 signal mc_ip_proto : std_logic_vector(7 downto 0);
402
403 attribute syn_preserve : boolean;
404 attribute syn_keep : boolean;
405 attribute syn_keep of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true;
406 attribute syn_preserve of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true;
407
408 signal pcs_txd_q, pcs_rxd_q : std_logic_vector(7 downto 0);
409 signal pcs_tx_en_q, pcs_tx_er_q, pcs_rx_en_q, pcs_rx_er_q, mac_col_q, mac_crs_q : std_logic;
410
411 signal pcs_txd_qq, pcs_rxd_qq : std_logic_vector(7 downto 0);
412 signal pcs_tx_en_qq, pcs_tx_er_qq, pcs_rx_en_qq, pcs_rx_er_qq, mac_col_qq, mac_crs_qq : std_logic;
413
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414 signal fc_test_rd_en, fc_test_rd_en_q : std_logic;
415 signal fr_rx_clk : std_logic;
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416 signal serdes_rx_clk_a, serdes_clk_125_a : std_logic;
417
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418 begin
419
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420 -- WARNING: setting allowed types to constat true
421 fr_allowed_types <= x"0000_00ff"; -- only test protocol allowed
422 fr_allowed_ip <= x"0000_00ff";
423 fr_allowed_udp <= x"0000_00ff";
424 vlan_id <= (others => '0');
425
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426 MAIN_CONTROL : trb_net16_gbe_main_control
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427 generic map ( g_GENERATE_STAT => g_GENERATE_STAT)
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428 port map(
429 CLK => CLKSYS_IN,
430 CLK_125 => CLKGBE_IN,
431 RESET => RESET,
432
433 MC_LINK_OK_OUT => link_ok,
434 MC_RESET_LINK_IN => '0',
435
436 -- signals to/from receive controller
437 RC_FRAME_WAITING_IN => rc_frame_ready,
438 RC_LOADING_DONE_OUT => rc_loading_done,
439 RC_DATA_IN => rc_q,
440 RC_RD_EN_OUT => rc_rd_en,
441 RC_FRAME_SIZE_IN => rc_frame_size,
442 RC_FRAME_PROTO_IN => rc_frame_proto,
443
444 RC_SRC_MAC_ADDRESS_IN => rc_src_mac,
445 RC_DEST_MAC_ADDRESS_IN => rc_dest_mac,
446 RC_SRC_IP_ADDRESS_IN => rc_src_ip,
447 RC_DEST_IP_ADDRESS_IN => rc_dest_ip,
448 RC_SRC_UDP_PORT_IN => rc_src_udp,
449 RC_DEST_UDP_PORT_IN => rc_dest_udp,
450
451 -- signals to/from transmit controller
452 TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl,
453 TC_TRANSMIT_DATA_OUT => mc_transmit_data,
454 TC_DATA_OUT => mc_data,
455 TC_RD_EN_IN => mc_rd_en,
456 TC_FRAME_SIZE_OUT => mc_frame_size,
457 TC_FRAME_TYPE_OUT => mc_type,
458 TC_IP_PROTOCOL_OUT => mc_ip_proto,
459
460 TC_DEST_MAC_OUT => mc_dest_mac,
461 TC_DEST_IP_OUT => mc_dest_ip,
462 TC_DEST_UDP_OUT => mc_dest_udp,
463 TC_SRC_MAC_OUT => mc_src_mac,
464 TC_SRC_IP_OUT => mc_src_ip,
465 TC_SRC_UDP_OUT => mc_src_udp,
466
467 TC_BUSY_IN => mc_busy,
468 TC_TRANSMIT_DONE_IN => mc_transmit_done,
469
470 -- signals to/from packet constructor
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471 PC_READY_IN => '1',
472 PC_TRANSMIT_ON_IN => '0',
473 PC_SOD_IN => '0',
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474
475 -- signals to/from sgmii/gbe pcs_an_complete
476 PCS_AN_COMPLETE_IN => pcs_an_complete,
477
478 -- signals to/from hub
479 MC_UNIQUE_ID_IN => (others => '0'),
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480
481 CNT_GENERATE_PACKET_IN => GENERATE_PACKET_IN,
482 CNT_TIMESTAMP_IN => TIMESTAMP_IN,
483 CNT_DEST_ADDR_IN => DEST_ADDR_IN,
484 CNT_SIZE_IN => SIZE_IN,
485 CNT_BUSY_OUT => BUSY_OUT,
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486
487 CNT_MODULE_SELECT_OUT => MODULE_SELECT_OUT,
488 CNT_MODULE_RD_EN_OUT => MODULE_RD_EN_OUT,
489 CNT_MODULE_DATA_IN => MODULE_DATA_IN,
490 CNT_STOP_TRANSMISSION_OUT => STOP_TRANSMISSION_OUT,
491 CNT_START_STAT_IN => START_STAT_IN,
492
493 CNT_MODULE_DATA_OUT => MODULE_DATA_OUT,
494 CNT_MODULE_RD_EN_IN => MODULE_RD_EN_IN,
495 CNT_MODULE_SELECTED_IN => MODULE_SELECTED_IN,
496 CNT_MODULE_FULL_OUT => MODULE_FULL_OUT,
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497 CNT_MODULE_ID_IN => MAC_ADDR_IN(3 downto 0),
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498
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499 GSC_CLK_IN => '0',
500 GSC_INIT_DATAREADY_OUT => open,
501 GSC_INIT_DATA_OUT => open,
502 GSC_INIT_PACKET_NUM_OUT => open,
503 GSC_INIT_READ_IN => '0',
504 GSC_REPLY_DATAREADY_IN => '0',
505 GSC_REPLY_DATA_IN => (others => '0'),
506 GSC_REPLY_PACKET_NUM_IN => (others => '0'),
507 GSC_REPLY_READ_OUT => open,
508 GSC_BUSY_IN => '0',
509
510 -- signal to/from Host interface of TriSpeed MAC
511 TSM_HADDR_OUT => mac_haddr,
512 TSM_HDATA_OUT => mac_hdataout,
513 TSM_HCS_N_OUT => mac_hcs,
514 TSM_HWRITE_N_OUT => mac_hwrite,
515 TSM_HREAD_N_OUT => mac_hread,
516 TSM_HREADY_N_IN => mac_hready,
517 TSM_HDATA_EN_N_IN => mac_hdata_en,
518 TSM_RX_STAT_VEC_IN => mac_rx_stat_vec,
519 TSM_RX_STAT_EN_IN => mac_rx_stat_en,
520
521 SELECT_REC_FRAMES_OUT => open,
522 SELECT_SENT_FRAMES_OUT => open,
523 SELECT_PROTOS_DEBUG_OUT => open,
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524
525 CNTRL_PACKET_SIZE_OUT => CNTRL_PACKET_SIZE_OUT,
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526
527 DEBUG_OUT => open
528 );
529
530
531 TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control
532 port map(
533 CLK => CLKSYS_IN,
534 RESET => RESET,
535
536 -- signals to/from packet constructor
537 PC_READY_IN => pc_ready,
538 PC_DATA_IN => tc_data,
539 PC_WR_EN_IN => tc_wr_en,
540 PC_IP_SIZE_IN => tc_ip_size,
541 PC_UDP_SIZE_IN => tc_udp_size,
542 PC_FLAGS_OFFSET_IN => tc_flags_offset,
543 PC_SOD_IN => tc_sod,
544 PC_EOD_IN => tc_eod,
545 PC_FC_READY_OUT => tc_pc_ready,
546 PC_FC_H_READY_OUT => tc_pc_h_ready,
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547 PC_TRANSMIT_ON_IN => '0',
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548
549 -- signals from ip_configurator used by packet constructor
550 IC_DEST_MAC_ADDRESS_IN => ic_dest_mac,
551 IC_DEST_IP_ADDRESS_IN => ic_dest_ip,
552 IC_DEST_UDP_PORT_IN => ic_dest_udp,
553 IC_SRC_MAC_ADDRESS_IN => ic_src_mac,
554 IC_SRC_IP_ADDRESS_IN => ic_src_ip,
555 IC_SRC_UDP_PORT_IN => ic_src_udp,
556
557 -- signal to/from main controller
558 MC_TRANSMIT_CTRL_IN => mc_transmit_ctrl,
559 MC_TRANSMIT_DATA_IN => mc_transmit_data,
560 MC_DATA_IN => mc_data,
561 MC_RD_EN_OUT => mc_rd_en,
562 MC_FRAME_SIZE_IN => mc_frame_size,
563 MC_FRAME_TYPE_IN => mc_type,
564 MC_IP_PROTOCOL_IN => mc_ip_proto,
565
566 MC_DEST_MAC_IN => mc_dest_mac,
567 MC_DEST_IP_IN => mc_dest_ip,
568 MC_DEST_UDP_IN => mc_dest_udp,
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569 MC_SRC_MAC_IN => MAC_ADDR_IN, --mc_src_mac, to identify the module
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570 MC_SRC_IP_IN => mc_src_ip,
571 MC_SRC_UDP_IN => mc_src_udp,
572
573 MC_BUSY_OUT => mc_busy,
574 MC_TRANSMIT_DONE_OUT => mc_transmit_done,
575
576 -- signal to/from frame constructor
577 FC_DATA_OUT => fc_data,
578 FC_WR_EN_OUT => fc_wr_en,
579 FC_READY_IN => fc_ready,
580 FC_H_READY_IN => fc_h_ready,
581 FC_FRAME_TYPE_OUT => fc_type,
582 FC_IP_SIZE_OUT => fc_ip_size,
583 FC_UDP_SIZE_OUT => fc_udp_size,
584 FC_IDENT_OUT => fc_ident,
585 FC_FLAGS_OFFSET_OUT => fc_flags_offset,
586 FC_SOD_OUT => fc_sod,
587 FC_EOD_OUT => fc_eod,
588 FC_IP_PROTOCOL_OUT => fc_protocol,
589
590 DEST_MAC_ADDRESS_OUT => fc_dest_mac,
591 DEST_IP_ADDRESS_OUT => fc_dest_ip,
592 DEST_UDP_PORT_OUT => fc_dest_udp,
593 SRC_MAC_ADDRESS_OUT => fc_src_mac,
594 SRC_IP_ADDRESS_OUT => fc_src_ip,
595 SRC_UDP_PORT_OUT => fc_src_udp,
596
597
598 -- debug
599 DEBUG_OUT => open
600 );
601
602 -- Third stage: Frame Constructor
603 FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr
604 port map(
605 -- ports for user logic
606 RESET => RESET,
607 CLK => CLKSYS_IN,
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608 LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
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609 --
610 WR_EN_IN => fc_wr_en,
611 DATA_IN => fc_data,
612 START_OF_DATA_IN => fc_sod,
613 END_OF_DATA_IN => fc_eod,
614 IP_F_SIZE_IN => fc_ip_size,
615 UDP_P_SIZE_IN => fc_udp_size,
616 HEADERS_READY_OUT => fc_h_ready,
617 READY_OUT => fc_ready,
618 DEST_MAC_ADDRESS_IN => fc_dest_mac,
619 DEST_IP_ADDRESS_IN => fc_dest_ip,
620 DEST_UDP_PORT_IN => fc_dest_udp,
621 SRC_MAC_ADDRESS_IN => fc_src_mac,
622 SRC_IP_ADDRESS_IN => fc_src_ip,
623 SRC_UDP_PORT_IN => fc_src_udp,
624 FRAME_TYPE_IN => fc_type,
625 IHL_VERSION_IN => fc_ihl_version,
626 TOS_IN => fc_tos,
627 IDENTIFICATION_IN => fc_ident,
628 FLAGS_OFFSET_IN => fc_flags_offset,
629 TTL_IN => fc_ttl,
630 PROTOCOL_IN => fc_protocol,
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631 FRAME_DELAY_IN => (others => '0'), -- gk 09.12.10
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632 -- ports for packetTransmitter
633 RD_CLK => serdes_clk_125,
634 FT_DATA_OUT => ft_data,
635 FT_TX_EMPTY_OUT => ft_tx_empty,
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636 FT_TX_RD_EN_IN => mac_tx_read,
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637 FT_START_OF_PACKET_OUT => ft_start_of_packet,
638 FT_TX_DONE_IN => mac_tx_done,
639 FT_TX_DISCFRM_IN => mac_tx_discfrm,
640 -- debug ports
641 BSM_CONSTR_OUT => open,
642 BSM_TRANS_OUT => open,
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643 DEBUG_OUT => open
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644 );
645
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646 fc_ttl <= x"10";
647
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648 RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
649 port map(
650 CLK => CLKSYS_IN,
651 RESET => RESET,
652
653 -- signals to/from frame_receiver
654 RC_DATA_IN => fr_q,
655 FR_RD_EN_OUT => fr_rd_en,
656 FR_FRAME_VALID_IN => fr_frame_valid,
657 FR_GET_FRAME_OUT => fr_get_frame,
658 FR_FRAME_SIZE_IN => fr_frame_size,
659 FR_FRAME_PROTO_IN => fr_frame_proto,
660 FR_IP_PROTOCOL_IN => fr_ip_proto,
661
662 FR_SRC_MAC_ADDRESS_IN => fr_src_mac,
663 FR_DEST_MAC_ADDRESS_IN => fr_dest_mac,
664 FR_SRC_IP_ADDRESS_IN => fr_src_ip,
665 FR_DEST_IP_ADDRESS_IN => fr_dest_ip,
666 FR_SRC_UDP_PORT_IN => fr_src_udp,
667 FR_DEST_UDP_PORT_IN => fr_dest_udp,
668
669 -- signals to/from main controller
670 RC_RD_EN_IN => rc_rd_en,
671 RC_Q_OUT => rc_q,
672 RC_FRAME_WAITING_OUT => rc_frame_ready,
673 RC_LOADING_DONE_IN => rc_loading_done,
674 RC_FRAME_SIZE_OUT => rc_frame_size,
675 RC_FRAME_PROTO_OUT => rc_frame_proto,
676
677 RC_SRC_MAC_ADDRESS_OUT => rc_src_mac,
678 RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac,
679 RC_SRC_IP_ADDRESS_OUT => rc_src_ip,
680 RC_DEST_IP_ADDRESS_OUT => rc_dest_ip,
681 RC_SRC_UDP_PORT_OUT => rc_src_udp,
682 RC_DEST_UDP_PORT_OUT => rc_dest_udp,
683
684 -- statistics
685 FRAMES_RECEIVED_OUT => open,
686 BYTES_RECEIVED_OUT => open,
687
688
689 DEBUG_OUT => open
690 );
691
692
693 FRAME_TRANSMITTER: trb_net16_gbe_frame_trans
694 port map(
695 CLK => CLKSYS_IN,
696 RESET => RESET,
697 LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
698 TX_MAC_CLK => serdes_clk_125,
699 TX_EMPTY_IN => ft_tx_empty,
700 START_OF_PACKET_IN => ft_start_of_packet,
701 DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10
702
703 TX_FIFOAVAIL_OUT => mac_fifoavail,
704 TX_FIFOEOF_OUT => mac_fifoeof,
705 TX_FIFOEMPTY_OUT => mac_fifoempty,
706 TX_DONE_IN => mac_tx_done,
707 TX_STAT_EN_IN => mac_tx_staten,
708 TX_STATVEC_IN => mac_tx_statevec,
709 TX_DISCFRM_IN => mac_tx_discfrm,
710 -- Debug
711 BSM_INIT_OUT => open,
712 BSM_MAC_OUT => open,
713 BSM_TRANS_OUT => open,
714 DBG_RD_DONE_OUT => open,
715 DBG_INIT_DONE_OUT => open,
716 DBG_ENABLED_OUT => open,
717 DEBUG_OUT => open
718 );
719
720
721 FRAME_RECEIVER : trb_net16_gbe_frame_receiver
722 port map(
723 CLK => CLKSYS_IN,
724 RESET => RESET,
725 LINK_OK_IN => link_ok,
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726 ALLOW_RX_IN => '1', --allow_rx,
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727 RX_MAC_CLK => serdes_rx_clk,
728
729 -- input signals from TS_MAC
730 MAC_RX_EOF_IN => mac_rx_eof,
731 MAC_RX_ER_IN => mac_rx_er,
732 MAC_RXD_IN => mac_rxd,
733 MAC_RX_EN_IN => mac_rx_en,
734 MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err,
735 MAC_RX_FIFO_FULL_OUT => mac_rx_fifo_full,
736 MAC_RX_STAT_EN_IN => mac_rx_stat_en,
737 MAC_RX_STAT_VEC_IN => mac_rx_stat_vec,
738 -- output signal to control logic
739 FR_Q_OUT => fr_q,
740 FR_RD_EN_IN => fr_rd_en,
741 FR_FRAME_VALID_OUT => fr_frame_valid,
742 FR_GET_FRAME_IN => fr_get_frame,
743 FR_FRAME_SIZE_OUT => fr_frame_size,
744 FR_FRAME_PROTO_OUT => fr_frame_proto,
745 FR_IP_PROTOCOL_OUT => fr_ip_proto,
746 FR_ALLOWED_TYPES_IN => fr_allowed_types,
747 FR_ALLOWED_IP_IN => fr_allowed_ip,
748 FR_ALLOWED_UDP_IN => fr_allowed_udp,
749 FR_VLAN_ID_IN => vlan_id,
750
751 FR_SRC_MAC_ADDRESS_OUT => fr_src_mac,
752 FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac,
753 FR_SRC_IP_ADDRESS_OUT => fr_src_ip,
754 FR_DEST_IP_ADDRESS_OUT => fr_dest_ip,
755 FR_SRC_UDP_PORT_OUT => fr_src_udp,
756 FR_DEST_UDP_PORT_OUT => fr_dest_udp,
757
758 DEBUG_OUT => open
759 );
760
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761 serdes_rx_clk <= CLKGBE_IN when g_SIMULATE = 1 else serdes_rx_clk_a;
762 serdes_clk_125 <= CLKGBE_IN when g_SIMULATE = 1 else serdes_clk_125_a;
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763
764 MAC: tsmac34
765 port map(
766 ----------------- clock and reset port declarations ------------------
767 hclk => CLKSYS_IN,
768 txmac_clk => serdes_clk_125,
769 rxmac_clk => serdes_rx_clk, --serdes_clk_125,
770 reset_n => GSR_N,
771 txmac_clk_en => mac_tx_clk_en,
772 rxmac_clk_en => mac_rx_clk_en,
773 ------------------- Input signals to the GMII ---------------- NOT USED
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774 rxd => pcs_rxd_qq,
775 rx_dv => pcs_rx_en_qq,
776 rx_er => pcs_rx_er_qq,
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777 col => mac_col,
778 crs => mac_crs,
779 -------------------- Input signals to the CPU I/F -------------------
780 haddr => mac_haddr,
781 hdatain => mac_hdataout,
782 hcs_n => mac_hcs,
783 hwrite_n => mac_hwrite,
784 hread_n => mac_hread,
785 ---------------- Input signals to the Tx MAC FIFO I/F ---------------
786 tx_fifodata => ft_data(7 downto 0),
787 tx_fifoavail => mac_fifoavail,
788 tx_fifoeof => mac_fifoeof,
789 tx_fifoempty => mac_fifoempty,
790 tx_sndpaustim => x"0000",
791 tx_sndpausreq => '0',
792 tx_fifoctrl => '0', -- always data frame
793 ---------------- Input signals to the Rx MAC FIFO I/F ---------------
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794 rx_fifo_full => mac_rx_fifo_full,
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795 ignore_pkt => '0',
796 ---------------- Output signals from the GMII -----------------------
797 txd => pcs_txd,
798 tx_en => pcs_tx_en,
799 tx_er => pcs_tx_er,
800 ----------------- Output signals from the CPU I/F -------------------
801 hdataout => open,
802 hdataout_en_n => mac_hdata_en,
803 hready_n => mac_hready,
804 cpu_if_gbit_en => tsmac_gbit_en,
805 ------------- Output signals from the Tx MAC FIFO I/F ---------------
806 tx_macread => mac_tx_read,
807 tx_discfrm => mac_tx_discfrm,
808 tx_staten => mac_tx_staten, -- gk 08.06.10
809 tx_statvec => mac_tx_statevec, -- gk 08.06.10
810 tx_done => mac_tx_done,
811 ------------- Output signals from the Rx MAC FIFO I/F ---------------
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812 rx_fifo_error => mac_rx_fifo_err,
813 rx_stat_vector => mac_rx_stat_vec,
814 rx_dbout => mac_rxd,
815 rx_write => mac_rx_en,
816 rx_stat_en => mac_rx_stat_en,
817 rx_eof => mac_rx_eof,
818 rx_error => mac_rx_er
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819 );
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820
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821
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822 SYNC_GMII_RX_PROC : process(serdes_rx_clk)
823 begin
824 if rising_edge(serdes_rx_clk) then
825 pcs_rxd_q <= pcs_rxd;
826 pcs_rx_en_q <= pcs_rx_en;
827 pcs_rx_er_q <= pcs_rx_er;
828
829 pcs_rxd_qq <= pcs_rxd_q;
830 pcs_rx_en_qq <= pcs_rx_en_q;
831 pcs_rx_er_qq <= pcs_rx_er_q;
832 end if;
833 end process SYNC_GMII_RX_PROC;
834
835 SYNC_GMII_TX_PROC : process(serdes_clk_125)
836 begin
837 if rising_edge(serdes_clk_125) then
838 pcs_txd_q <= pcs_txd;
839 pcs_tx_en_q <= pcs_tx_en;
840 pcs_tx_er_q <= pcs_tx_er;
841
842 pcs_txd_qq <= pcs_txd_q;
843 pcs_tx_en_qq <= pcs_tx_en_q;
844 pcs_tx_er_qq <= pcs_tx_er_q;
845 end if;
846 end process SYNC_GMII_TX_PROC;
847
848 PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b
849 generic map(
850 USE_125MHZ_EXTCLK => 0
851 )
852 port map(
853 RESET => RESET,
854 GSR_N => GSR_N,
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855 CLK_125_OUT => serdes_clk_125_a,
856 CLK_125_RX_OUT => serdes_rx_clk_a,
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857 CLK_125_IN => CLKGBE_IN,
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858 FT_TX_CLK_EN_OUT => mac_tx_clk_en,
859 FT_RX_CLK_EN_OUT => mac_rx_clk_en,
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860 --connection to frame transmitter (tsmac)
861 FT_COL_OUT => mac_col,
862 FT_CRS_OUT => mac_crs,
863 FT_TXD_IN => pcs_txd_qq,
864 FT_TX_EN_IN => pcs_tx_en_qq,
865 FT_TX_ER_IN => pcs_tx_er_qq,
866 FT_RXD_OUT => pcs_rxd,
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867 FT_RX_EN_OUT => pcs_rx_en,
868 FT_RX_ER_OUT => pcs_rx_er,
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869
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870 -- Autonegotiation stuff
871 MR_ADV_ABILITY_IN => x"0020", -- full duplex only
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872 MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability,
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873 MR_AN_PAGE_RX_OUT => pcs_an_page_rx,
874 MR_AN_COMPLETE_OUT => pcs_an_complete,
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875 MR_RESET_IN => RESET,
876 MR_MODE_IN => '0', --MR_MODE_IN,
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877 MR_AN_ENABLE_IN => '0', -- do autonegotiation
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878 MR_RESTART_AN_IN => '0', --MR_RESTART_IN,
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879
880 SD_RX_CLK_IN => SD_RX_CLK_IN,
881 SD_TX_DATA_OUT => SD_TX_DATA_OUT,
882 SD_TX_KCNTL_OUT => SD_TX_KCNTL_OUT,
883 SD_TX_CORRECT_DISP_OUT => SD_TX_CORRECT_DISP_OUT,
884 SD_RX_DATA_IN => SD_RX_DATA_IN,
885 SD_RX_KCNTL_IN => SD_RX_KCNTL_IN,
886 SD_RX_DISP_ERROR_IN => SD_RX_DISP_ERROR_IN,
887 SD_RX_CV_ERROR_IN => SD_RX_CV_ERROR_IN,
888 SD_RX_SERDES_RST_OUT => SD_RX_SERDES_RST_OUT,
889 SD_RX_PCS_RST_OUT => SD_RX_PCS_RST_OUT,
890 SD_TX_PCS_RST_OUT => SD_TX_PCS_RST_OUT,
891 SD_RX_LOS_IN => SD_RX_LOS_IN,
892 SD_SIGNAL_DETECTED_IN => SD_SIGNAL_DETECTED_IN,
893 SD_RX_CDR_IN => SD_RX_CDR_IN,
894 SD_TX_PLL_LOL_IN => SD_TX_PLL_LOL_IN,
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895 SD_QUAD_RST_OUT => SD_QUAD_RST_OUT,
896 SD_XMIT_OUT => SD_XMIT_OUT
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897 );
898
899
900 -- FrameConstructor fixed magic values
901 --fc_type <= x"0008";
902 fc_ihl_version <= x"45";
903 fc_tos <= x"10";
904
905 -- FrameConstructor fixed magic values
906 --fc_type <= x"0008";
907 fc_ihl_version <= x"45";
908 fc_tos <= x"10";
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909
910 LINK_OK_OUT <= link_ok;
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911
912
913 -- for debug only
914 --TEST_PORT_OUT(7 downto 0) <= ft_data;
915 --TEST_PORT_OUT(8) <= mac_fifoeof;
916 --TEST_PORT_OUT(9) <= mac_fifoavail;
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917
918 end architecture CNTester_module;
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