Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with
or
.
Download ZIP
Newer
Older
100644 900 lines (788 sloc) 32.88 kB
a53c7d0 first commit
grzegorzkorcyl authored
1 LIBRARY ieee;
2 use ieee.std_logic_1164.all;
3 USE IEEE.numeric_std.ALL;
4 USE IEEE.std_logic_UNSIGNED.ALL;
5 use IEEE.std_logic_arith.all;
6
7 library work;
8 use work.trb_net_std.all;
9 use work.trb_net_components.all;
10 use work.trb_net16_hub_func.all;
11
12 use work.trb_net_gbe_components.all;
13 use work.trb_net_gbe_protocols.all;
14
15 entity CNTester_module is
b3e9a1b update
grzegorzkorcyl authored
16 generic ( g_GENERATE_STAT : integer range 0 to 1 := 0);
a53c7d0 first commit
grzegorzkorcyl authored
17 port (
18 CLKSYS_IN : in std_logic;
19 CLKGBE_IN : in std_logic;
20 RESET : in std_logic;
21 GSR_N : in std_logic;
18c5bab update
grzegorzkorcyl authored
22 LINK_OK_OUT : out std_logic;
a53c7d0 first commit
grzegorzkorcyl authored
23
848a879 update
grzegorzkorcyl authored
24 MAC_ADDR_IN : in std_logic_vector(47 downto 0);
a53c7d0 first commit
grzegorzkorcyl authored
25 TIMESTAMP_IN : in std_logic_vector(31 downto 0);
26 DEST_ADDR_IN : in std_logic_vector(15 downto 0);
8aa25b8 update
grzegorzkorcyl authored
27 GENERATE_PACKET_IN : in std_logic;
e88e265 update
grzegorzkorcyl authored
28 SIZE_IN : in std_logic_vector(15 downto 0);
29 BUSY_OUT : out std_logic;
8aa25b8 update
grzegorzkorcyl authored
30
b3e9a1b update
grzegorzkorcyl authored
31 MODULE_SELECT_OUT : out std_logic_vector(7 downto 0);
32 MODULE_RD_EN_OUT : out std_logic;
33 MODULE_DATA_IN : in std_logic_vector(71 downto 0);
34 STOP_TRANSMISSION_OUT : out std_logic;
35 START_STAT_IN : in std_logic;
36
37 MODULE_DATA_OUT : out std_logic_vector(71 downto 0);
38 MODULE_RD_EN_IN : in std_logic;
39 MODULE_SELECTED_IN : in std_logic;
40 MODULE_FULL_OUT : out std_logic;
41
e88e265 update
grzegorzkorcyl authored
42 -- serdes io
43 SD_RX_CLK_IN : in std_logic;
44 SD_TX_DATA_OUT : out std_logic_vector(7 downto 0);
45 SD_TX_KCNTL_OUT : out std_logic;
46 SD_TX_CORRECT_DISP_OUT : out std_logic;
47 SD_RX_DATA_IN : in std_logic_vector(7 downto 0);
48 SD_RX_KCNTL_IN : in std_logic;
49 SD_RX_DISP_ERROR_IN : in std_logic;
50 SD_RX_CV_ERROR_IN : in std_logic;
51 SD_RX_SERDES_RST_OUT : out std_logic;
52 SD_RX_PCS_RST_OUT : out std_logic;
53 SD_TX_PCS_RST_OUT : out std_logic;
54 SD_RX_LOS_IN : in std_logic;
55 SD_SIGNAL_DETECTED_IN : in std_logic;
56 SD_RX_CDR_IN : in std_logic;
57 SD_TX_PLL_LOL_IN : in std_logic;
5e3450e update
grzegorzkorcyl authored
58 SD_QUAD_RST_OUT : out std_logic;
59 SD_XMIT_OUT : out std_logic
a53c7d0 first commit
grzegorzkorcyl authored
60 );
61 end entity CNTester_module;
62
63 architecture CNTester_module of CNTester_module is
64
65
66 component tsmac34
67 port(
68 --------------- clock and reset port declarations ------------------
69 hclk : in std_logic;
70 txmac_clk : in std_logic;
71 rxmac_clk : in std_logic;
72 reset_n : in std_logic;
73 txmac_clk_en : in std_logic;
74 rxmac_clk_en : in std_logic;
75 ------------------- Input signals to the GMII ----------------
76 rxd : in std_logic_vector(7 downto 0);
77 rx_dv : in std_logic;
78 rx_er : in std_logic;
79 col : in std_logic;
80 crs : in std_logic;
81 -------------------- Input signals to the CPU I/F -------------------
82 haddr : in std_logic_vector(7 downto 0);
83 hdatain : in std_logic_vector(7 downto 0);
84 hcs_n : in std_logic;
85 hwrite_n : in std_logic;
86 hread_n : in std_logic;
87 ---------------- Input signals to the Tx MAC FIFO I/F ---------------
88 tx_fifodata : in std_logic_vector(7 downto 0);
89 tx_fifoavail : in std_logic;
90 tx_fifoeof : in std_logic;
91 tx_fifoempty : in std_logic;
92 tx_sndpaustim : in std_logic_vector(15 downto 0);
93 tx_sndpausreq : in std_logic;
94 tx_fifoctrl : in std_logic;
95 ---------------- Input signals to the Rx MAC FIFO I/F ---------------
96 rx_fifo_full : in std_logic;
97 ignore_pkt : in std_logic;
98 -------------------- Output signals from the GMII -----------------------
99 txd : out std_logic_vector(7 downto 0);
100 tx_en : out std_logic;
101 tx_er : out std_logic;
102 -------------------- Output signals from the CPU I/F -------------------
103 hdataout : out std_logic_vector(7 downto 0);
104 hdataout_en_n : out std_logic;
105 hready_n : out std_logic;
106 cpu_if_gbit_en : out std_logic;
107 ---------------- Output signals from the Tx MAC FIFO I/F ---------------
108 tx_macread : out std_logic;
109 tx_discfrm : out std_logic;
110 tx_staten : out std_logic;
111 tx_done : out std_logic;
112 tx_statvec : out std_logic_vector(30 downto 0);
113 ---------------- Output signals from the Rx MAC FIFO I/F ---------------
114 rx_fifo_error : out std_logic;
115 rx_stat_vector : out std_logic_vector(31 downto 0);
116 rx_dbout : out std_logic_vector(7 downto 0);
117 rx_write : out std_logic;
118 rx_stat_en : out std_logic;
119 rx_eof : out std_logic;
120 rx_error : out std_logic
121 );
122 end component;
123
124 --*********
125 -- MOST OF THE SIGNAL ARE NOT NEEDED, JUST COPIED FROM THE ORIGINAL BUF
126
127 signal pc_wr_en : std_logic;
128 signal pc_data : std_logic_vector(7 downto 0);
129 signal pc_eod : std_logic;
130 signal pc_sos : std_logic;
131 signal pc_ready : std_logic;
132 signal pc_padding : std_logic;
133 signal pc_decoding : std_logic_vector(31 downto 0);
134 signal pc_event_id : std_logic_vector(31 downto 0);
135 signal pc_queue_dec : std_logic_vector(31 downto 0);
136 signal pc_max_frame_size : std_logic_vector(15 downto 0);
137 signal pc_bsm_constr : std_logic_vector(3 downto 0);
138 signal pc_bsm_load : std_logic_vector(3 downto 0);
139 signal pc_bsm_save : std_logic_vector(3 downto 0);
140 signal pc_shf_empty : std_logic;
141 signal pc_shf_full : std_logic;
142 signal pc_shf_wr_en : std_logic;
143 signal pc_shf_rd_en : std_logic;
144 signal pc_shf_q : std_logic_vector(7 downto 0);
145 signal pc_df_empty : std_logic;
146 signal pc_df_full : std_logic;
147 signal pc_df_wr_en : std_logic;
148 signal pc_df_rd_en : std_logic;
149 signal pc_df_q : std_logic_vector(7 downto 0);
150 signal pc_all_ctr : std_logic_vector(4 downto 0);
151 signal pc_sub_ctr : std_logic_vector(4 downto 0);
152 signal pc_bytes_loaded : std_logic_vector(15 downto 0);
153 signal pc_size_left : std_logic_vector(31 downto 0);
154 signal pc_sub_size_to_save : std_logic_vector(31 downto 0);
155 signal pc_sub_size_loaded : std_logic_vector(31 downto 0);
156 signal pc_sub_bytes_loaded : std_logic_vector(31 downto 0);
157 signal pc_queue_size : std_logic_vector(31 downto 0);
158 signal pc_act_queue_size : std_logic_vector(31 downto 0);
159
160 signal fee_read : std_logic;
161 signal cts_readout_finished : std_logic;
162 signal cts_dataready : std_logic;
163 signal cts_length : std_logic_vector(15 downto 0);
164 signal cts_data : std_logic_vector(31 downto 0); -- DHDR of rest packet
165 signal cts_error_pattern : std_logic_vector(31 downto 0);
166
167 signal pc_sub_size : std_logic_vector(31 downto 0);
168 signal pc_trig_nr : std_logic_vector(31 downto 0);
169
170 signal tc_wr_en : std_logic;
171 signal tc_data : std_logic_vector(7 downto 0);
172 signal tc_ip_size : std_logic_vector(15 downto 0);
173 signal tc_udp_size : std_logic_vector(15 downto 0);
174 signal tc_ident : std_logic_vector(15 downto 0);
175 signal tc_flags_offset : std_logic_vector(15 downto 0);
176 signal tc_sod : std_logic;
177 signal tc_eod : std_logic;
178 signal tc_h_ready : std_logic;
179 signal tc_ready : std_logic;
180 signal fc_dest_mac : std_logic_vector(47 downto 0);
181 signal fc_dest_ip : std_logic_vector(31 downto 0);
182 signal fc_dest_udp : std_logic_vector(15 downto 0);
183 signal fc_src_mac : std_logic_vector(47 downto 0);
184 signal fc_src_ip : std_logic_vector(31 downto 0);
185 signal fc_src_udp : std_logic_vector(15 downto 0);
186 signal fc_type : std_logic_vector(15 downto 0);
187 signal fc_ihl_version : std_logic_vector(7 downto 0);
188 signal fc_tos : std_logic_vector(7 downto 0);
189 signal fc_ttl : std_logic_vector(7 downto 0);
190 signal fc_protocol : std_logic_vector(7 downto 0);
191 signal fc_bsm_constr : std_logic_vector(7 downto 0);
192 signal fc_bsm_trans : std_logic_vector(3 downto 0);
193
194 signal ft_data : std_logic_vector(8 downto 0);-- gk 04.05.10
195 signal ft_tx_empty : std_logic;
196 signal ft_start_of_packet : std_logic;
197 signal ft_bsm_init : std_logic_vector(3 downto 0);
198 signal ft_bsm_mac : std_logic_vector(3 downto 0);
199 signal ft_bsm_trans : std_logic_vector(3 downto 0);
200
201 signal mac_haddr : std_logic_vector(7 downto 0);
202 signal mac_hdataout : std_logic_vector(7 downto 0);
203 signal mac_hcs : std_logic;
204 signal mac_hwrite : std_logic;
205 signal mac_hread : std_logic;
206 signal mac_fifoavail : std_logic;
207 signal mac_fifoempty : std_logic;
208 signal mac_fifoeof : std_logic;
209 signal mac_hready : std_logic;
210 signal mac_hdata_en : std_logic;
211 signal mac_tx_done : std_logic;
212 signal mac_tx_read : std_logic;
213
214 signal serdes_clk_125 : std_logic;
215 signal mac_tx_clk_en : std_logic;
216 signal mac_rx_clk_en : std_logic;
217 signal mac_col : std_logic;
218 signal mac_crs : std_logic;
219 signal pcs_txd : std_logic_vector(7 downto 0);
220 signal pcs_tx_en : std_logic;
221 signal pcs_tx_er : std_logic;
222 signal pcs_an_lp_ability : std_logic_vector(15 downto 0);
223 signal pcs_an_complete : std_logic;
224 signal pcs_an_page_rx : std_logic;
225
226 signal pcs_stat_debug : std_logic_vector(63 downto 0);
227
228 signal stage_stat_regs : std_logic_vector(31 downto 0);
229 signal stage_ctrl_regs : std_logic_vector(31 downto 0);
230
231 signal analyzer_debug : std_logic_vector(63 downto 0);
232
233 signal ip_cfg_start : std_logic;
234 signal ip_cfg_bank : std_logic_vector(3 downto 0);
235 signal ip_cfg_done : std_logic;
236
237 signal ip_cfg_mem_addr : std_logic_vector(7 downto 0);
238 signal ip_cfg_mem_data : std_logic_vector(31 downto 0);
239 signal ip_cfg_mem_clk : std_logic;
240
241 -- gk 22.04.10
242 signal max_packet : std_logic_vector(31 downto 0);
243 signal min_packet : std_logic_vector(31 downto 0);
244 signal use_gbe : std_logic;
245 signal use_trbnet : std_logic;
246 signal use_multievents : std_logic;
247 -- gk 26.04.10
248 signal readout_ctr : std_logic_vector(23 downto 0);
249 signal readout_ctr_valid : std_logic;
250 signal gbe_trig_nr : std_logic_vector(31 downto 0);
251 -- gk 28.04.10
252 signal pc_delay : std_logic_vector(31 downto 0);
253 -- gk 04.05.10
254 signal ft_eod : std_logic;
255 -- gk 08.06.10
256 signal mac_tx_staten : std_logic;
257 signal mac_tx_statevec : std_logic_vector(30 downto 0);
258 signal mac_tx_discfrm : std_logic;
259
260 -- gk 21.07.10
261 signal allow_large : std_logic;
262
263 -- gk 28.07.10
264 signal bytes_sent_ctr : std_logic_vector(31 downto 0);
265 signal monitor_sent : std_logic_vector(31 downto 0);
266 signal monitor_dropped : std_logic_vector(31 downto 0);
267 signal monitor_sm : std_logic_vector(31 downto 0);
268 signal monitor_lr : std_logic_vector(31 downto 0);
269 signal monitor_hr : std_logic_vector(31 downto 0);
270 signal monitor_fifos : std_logic_vector(31 downto 0);
271 signal monitor_fifos_q : std_logic_vector(31 downto 0);
272 signal monitor_discfrm : std_logic_vector(31 downto 0);
273
274 -- gk 02.08.10
275 signal discfrm_ctr : std_logic_vector(31 downto 0);
276
277 -- gk 30.09.10
278 signal fc_rd_en : std_logic;
279 signal link_ok : std_logic;
280 signal link_ok_timeout_ctr : std_logic_vector(15 downto 0);
281
282 type linkStates is (ACTIVE, INACTIVE, TIMEOUT, FINALIZE);
283 signal link_current_state, link_next_state : linkStates;
284
285 signal link_down_ctr : std_logic_vector(15 downto 0);
286 signal link_down_ctr_lock : std_logic;
287
288 signal link_state : std_logic_vector(3 downto 0);
289
290 signal monitor_empty : std_logic_vector(31 downto 0);
291
292 -- gk 07.10.10
293 signal pc_eos : std_logic;
294
295 -- gk 09.12.10
296 signal frame_delay : std_logic_vector(31 downto 0);
297
298 -- gk 13.02.11
299 signal pcs_rxd : std_logic_vector(7 downto 0);
300 signal pcs_rx_en : std_logic;
301 signal pcs_rx_er : std_logic;
302 signal mac_rx_eof : std_logic;
303 signal mac_rx_er : std_logic;
304 signal mac_rxd : std_logic_vector(7 downto 0);
305 signal mac_rx_fifo_err : std_logic;
306 signal mac_rx_fifo_full : std_logic;
307 signal mac_rx_en : std_logic;
308 signal mac_rx_stat_en : std_logic;
309 signal mac_rx_stat_vec : std_logic_vector(31 downto 0);
310 signal fr_q : std_logic_vector(8 downto 0);
311 signal fr_rd_en : std_logic;
312 signal fr_frame_valid : std_logic;
313 signal rc_rd_en : std_logic;
314 signal rc_q : std_logic_vector(8 downto 0);
315 signal rc_frames_rec_ctr : std_logic_vector(31 downto 0);
316 signal tc_pc_ready : std_logic;
317 signal tc_pc_h_ready : std_logic;
318 signal mc_ctrl_frame_req : std_logic;
319 signal mc_data : std_logic_vector(8 downto 0);
320 signal mc_rd_en : std_logic;
321 signal fc_wr_en : std_logic;
322 signal fc_data : std_logic_vector(7 downto 0);
323 signal fc_ip_size : std_logic_vector(15 downto 0);
324 signal fc_udp_size : std_logic_vector(15 downto 0);
325 signal fc_ident : std_logic_vector(15 downto 0);
326 signal fc_flags_offset : std_logic_vector(15 downto 0);
327 signal fc_sod : std_logic;
328 signal fc_eod : std_logic;
329 signal fc_h_ready : std_logic;
330 signal fc_ready : std_logic;
331 signal rc_frame_ready : std_logic;
332 signal allow_rx : std_logic;
333 signal fr_frame_size : std_logic_vector(15 downto 0);
334 signal rc_frame_size : std_logic_vector(15 downto 0);
335 signal mc_frame_size : std_logic_vector(15 downto 0);
336 signal ic_dest_mac : std_logic_vector(47 downto 0);
337 signal ic_dest_ip : std_logic_vector(31 downto 0);
338 signal ic_dest_udp : std_logic_vector(15 downto 0);
339 signal ic_src_mac : std_logic_vector(47 downto 0);
340 signal ic_src_ip : std_logic_vector(31 downto 0);
341 signal ic_src_udp : std_logic_vector(15 downto 0);
342 signal pc_transmit_on : std_logic;
343 signal rc_bytes_rec : std_logic_vector(31 downto 0);
344 signal rc_debug : std_logic_vector(63 downto 0);
345 signal mc_busy : std_logic;
346 signal tsmac_gbit_en : std_logic;
347 signal mc_transmit_ctrl : std_logic;
348 signal mc_transmit_data : std_logic;
349 signal rc_loading_done : std_logic;
350 signal fr_get_frame : std_logic;
351 signal mc_transmit_done : std_logic;
352
353 signal dbg_fr : std_logic_vector(95 downto 0);
354 signal dbg_rc : std_logic_vector(63 downto 0);
355 signal dbg_mc : std_logic_vector(63 downto 0);
356 signal dbg_tc : std_logic_vector(63 downto 0);
357
358 signal fr_allowed_types : std_logic_vector(31 downto 0);
359 signal fr_allowed_ip : std_logic_vector(31 downto 0);
360 signal fr_allowed_udp : std_logic_vector(31 downto 0);
361
362 signal fr_frame_proto : std_logic_vector(15 downto 0);
363 signal rc_frame_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
364
365 signal dbg_select_rec : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
366 signal dbg_select_sent : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
367 signal dbg_select_protos : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
368
369 signal serdes_rx_clk : std_logic;
370
371 signal vlan_id : std_logic_vector(31 downto 0);
372 signal mc_type : std_logic_vector(15 downto 0);
373 signal fr_src_mac : std_logic_vector(47 downto 0);
374 signal fr_dest_mac : std_logic_vector(47 downto 0);
375 signal fr_src_ip : std_logic_vector(31 downto 0);
376 signal fr_dest_ip : std_logic_vector(31 downto 0);
377 signal fr_src_udp : std_logic_vector(15 downto 0);
378 signal fr_dest_udp : std_logic_vector(15 downto 0);
379 signal rc_src_mac : std_logic_vector(47 downto 0);
380 signal rc_dest_mac : std_logic_vector(47 downto 0);
381 signal rc_src_ip : std_logic_vector(31 downto 0);
382 signal rc_dest_ip : std_logic_vector(31 downto 0);
383 signal rc_src_udp : std_logic_vector(15 downto 0);
384 signal rc_dest_udp : std_logic_vector(15 downto 0);
385
386 signal mc_dest_mac : std_logic_vector(47 downto 0);
387 signal mc_dest_ip : std_logic_vector(31 downto 0);
388 signal mc_dest_udp : std_logic_vector(15 downto 0);
389 signal mc_src_mac : std_logic_vector(47 downto 0);
390 signal mc_src_ip : std_logic_vector(31 downto 0);
391 signal mc_src_udp : std_logic_vector(15 downto 0);
392
393 signal dbg_ft : std_logic_vector(63 downto 0);
394
395 signal fr_ip_proto : std_logic_vector(7 downto 0);
396 signal mc_ip_proto : std_logic_vector(7 downto 0);
397
398 attribute syn_preserve : boolean;
399 attribute syn_keep : boolean;
400 attribute syn_keep of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true;
401 attribute syn_preserve of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true;
402
403 signal pcs_txd_q, pcs_rxd_q : std_logic_vector(7 downto 0);
404 signal pcs_tx_en_q, pcs_tx_er_q, pcs_rx_en_q, pcs_rx_er_q, mac_col_q, mac_crs_q : std_logic;
405
406 signal pcs_txd_qq, pcs_rxd_qq : std_logic_vector(7 downto 0);
407 signal pcs_tx_en_qq, pcs_tx_er_qq, pcs_rx_en_qq, pcs_rx_er_qq, mac_col_qq, mac_crs_qq : std_logic;
408
b3e9a1b update
grzegorzkorcyl authored
409 signal fc_test_rd_en : std_logic;
a53c7d0 first commit
grzegorzkorcyl authored
410
411 begin
412
413 MAIN_CONTROL : trb_net16_gbe_main_control
b3e9a1b update
grzegorzkorcyl authored
414 generic map ( g_GENERATE_STAT => g_GENERATE_STAT)
a53c7d0 first commit
grzegorzkorcyl authored
415 port map(
416 CLK => CLKSYS_IN,
417 CLK_125 => CLKGBE_IN,
418 RESET => RESET,
419
420 MC_LINK_OK_OUT => link_ok,
421 MC_RESET_LINK_IN => '0',
422
423 -- signals to/from receive controller
424 RC_FRAME_WAITING_IN => rc_frame_ready,
425 RC_LOADING_DONE_OUT => rc_loading_done,
426 RC_DATA_IN => rc_q,
427 RC_RD_EN_OUT => rc_rd_en,
428 RC_FRAME_SIZE_IN => rc_frame_size,
429 RC_FRAME_PROTO_IN => rc_frame_proto,
430
431 RC_SRC_MAC_ADDRESS_IN => rc_src_mac,
432 RC_DEST_MAC_ADDRESS_IN => rc_dest_mac,
433 RC_SRC_IP_ADDRESS_IN => rc_src_ip,
434 RC_DEST_IP_ADDRESS_IN => rc_dest_ip,
435 RC_SRC_UDP_PORT_IN => rc_src_udp,
436 RC_DEST_UDP_PORT_IN => rc_dest_udp,
437
438 -- signals to/from transmit controller
439 TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl,
440 TC_TRANSMIT_DATA_OUT => mc_transmit_data,
441 TC_DATA_OUT => mc_data,
442 TC_RD_EN_IN => mc_rd_en,
443 TC_FRAME_SIZE_OUT => mc_frame_size,
444 TC_FRAME_TYPE_OUT => mc_type,
445 TC_IP_PROTOCOL_OUT => mc_ip_proto,
446
447 TC_DEST_MAC_OUT => mc_dest_mac,
448 TC_DEST_IP_OUT => mc_dest_ip,
449 TC_DEST_UDP_OUT => mc_dest_udp,
450 TC_SRC_MAC_OUT => mc_src_mac,
451 TC_SRC_IP_OUT => mc_src_ip,
452 TC_SRC_UDP_OUT => mc_src_udp,
453
454 TC_BUSY_IN => mc_busy,
455 TC_TRANSMIT_DONE_IN => mc_transmit_done,
456
457 -- signals to/from packet constructor
4ba8a13 update
grzegorzkorcyl authored
458 PC_READY_IN => '1',
459 PC_TRANSMIT_ON_IN => '0',
460 PC_SOD_IN => '0',
a53c7d0 first commit
grzegorzkorcyl authored
461
462 -- signals to/from sgmii/gbe pcs_an_complete
463 PCS_AN_COMPLETE_IN => pcs_an_complete,
464
465 -- signals to/from hub
466 MC_UNIQUE_ID_IN => (others => '0'),
e88e265 update
grzegorzkorcyl authored
467
468 CNT_GENERATE_PACKET_IN => GENERATE_PACKET_IN,
469 CNT_TIMESTAMP_IN => TIMESTAMP_IN,
470 CNT_DEST_ADDR_IN => DEST_ADDR_IN,
471 CNT_SIZE_IN => SIZE_IN,
472 CNT_BUSY_OUT => BUSY_OUT,
b3e9a1b update
grzegorzkorcyl authored
473
474 CNT_MODULE_SELECT_OUT => MODULE_SELECT_OUT,
475 CNT_MODULE_RD_EN_OUT => MODULE_RD_EN_OUT,
476 CNT_MODULE_DATA_IN => MODULE_DATA_IN,
477 CNT_STOP_TRANSMISSION_OUT => STOP_TRANSMISSION_OUT,
478 CNT_START_STAT_IN => START_STAT_IN,
479
480 CNT_MODULE_DATA_OUT => MODULE_DATA_OUT,
481 CNT_MODULE_RD_EN_IN => MODULE_RD_EN_IN,
482 CNT_MODULE_SELECTED_IN => MODULE_SELECTED_IN,
483 CNT_MODULE_FULL_OUT => MODULE_FULL_OUT,
e88e265 update
grzegorzkorcyl authored
484
a53c7d0 first commit
grzegorzkorcyl authored
485 GSC_CLK_IN => '0',
486 GSC_INIT_DATAREADY_OUT => open,
487 GSC_INIT_DATA_OUT => open,
488 GSC_INIT_PACKET_NUM_OUT => open,
489 GSC_INIT_READ_IN => '0',
490 GSC_REPLY_DATAREADY_IN => '0',
491 GSC_REPLY_DATA_IN => (others => '0'),
492 GSC_REPLY_PACKET_NUM_IN => (others => '0'),
493 GSC_REPLY_READ_OUT => open,
494 GSC_BUSY_IN => '0',
495
496 -- signal to/from Host interface of TriSpeed MAC
497 TSM_HADDR_OUT => mac_haddr,
498 TSM_HDATA_OUT => mac_hdataout,
499 TSM_HCS_N_OUT => mac_hcs,
500 TSM_HWRITE_N_OUT => mac_hwrite,
501 TSM_HREAD_N_OUT => mac_hread,
502 TSM_HREADY_N_IN => mac_hready,
503 TSM_HDATA_EN_N_IN => mac_hdata_en,
504 TSM_RX_STAT_VEC_IN => mac_rx_stat_vec,
505 TSM_RX_STAT_EN_IN => mac_rx_stat_en,
506
507 SELECT_REC_FRAMES_OUT => open,
508 SELECT_SENT_FRAMES_OUT => open,
509 SELECT_PROTOS_DEBUG_OUT => open,
510
511 DEBUG_OUT => open
512 );
513
514
515 TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control
516 port map(
517 CLK => CLKSYS_IN,
518 RESET => RESET,
519
520 -- signals to/from packet constructor
521 PC_READY_IN => pc_ready,
522 PC_DATA_IN => tc_data,
523 PC_WR_EN_IN => tc_wr_en,
524 PC_IP_SIZE_IN => tc_ip_size,
525 PC_UDP_SIZE_IN => tc_udp_size,
526 PC_FLAGS_OFFSET_IN => tc_flags_offset,
527 PC_SOD_IN => tc_sod,
528 PC_EOD_IN => tc_eod,
529 PC_FC_READY_OUT => tc_pc_ready,
530 PC_FC_H_READY_OUT => tc_pc_h_ready,
4ba8a13 update
grzegorzkorcyl authored
531 PC_TRANSMIT_ON_IN => '0',
a53c7d0 first commit
grzegorzkorcyl authored
532
533 -- signals from ip_configurator used by packet constructor
534 IC_DEST_MAC_ADDRESS_IN => ic_dest_mac,
535 IC_DEST_IP_ADDRESS_IN => ic_dest_ip,
536 IC_DEST_UDP_PORT_IN => ic_dest_udp,
537 IC_SRC_MAC_ADDRESS_IN => ic_src_mac,
538 IC_SRC_IP_ADDRESS_IN => ic_src_ip,
539 IC_SRC_UDP_PORT_IN => ic_src_udp,
540
541 -- signal to/from main controller
542 MC_TRANSMIT_CTRL_IN => mc_transmit_ctrl,
543 MC_TRANSMIT_DATA_IN => mc_transmit_data,
544 MC_DATA_IN => mc_data,
545 MC_RD_EN_OUT => mc_rd_en,
546 MC_FRAME_SIZE_IN => mc_frame_size,
547 MC_FRAME_TYPE_IN => mc_type,
548 MC_IP_PROTOCOL_IN => mc_ip_proto,
549
550 MC_DEST_MAC_IN => mc_dest_mac,
551 MC_DEST_IP_IN => mc_dest_ip,
552 MC_DEST_UDP_IN => mc_dest_udp,
848a879 update
grzegorzkorcyl authored
553 MC_SRC_MAC_IN => MAC_ADDR_IN, --mc_src_mac, to identify the module
a53c7d0 first commit
grzegorzkorcyl authored
554 MC_SRC_IP_IN => mc_src_ip,
555 MC_SRC_UDP_IN => mc_src_udp,
556
557 MC_BUSY_OUT => mc_busy,
558 MC_TRANSMIT_DONE_OUT => mc_transmit_done,
559
560 -- signal to/from frame constructor
561 FC_DATA_OUT => fc_data,
562 FC_WR_EN_OUT => fc_wr_en,
563 FC_READY_IN => fc_ready,
564 FC_H_READY_IN => fc_h_ready,
565 FC_FRAME_TYPE_OUT => fc_type,
566 FC_IP_SIZE_OUT => fc_ip_size,
567 FC_UDP_SIZE_OUT => fc_udp_size,
568 FC_IDENT_OUT => fc_ident,
569 FC_FLAGS_OFFSET_OUT => fc_flags_offset,
570 FC_SOD_OUT => fc_sod,
571 FC_EOD_OUT => fc_eod,
572 FC_IP_PROTOCOL_OUT => fc_protocol,
573
574 DEST_MAC_ADDRESS_OUT => fc_dest_mac,
575 DEST_IP_ADDRESS_OUT => fc_dest_ip,
576 DEST_UDP_PORT_OUT => fc_dest_udp,
577 SRC_MAC_ADDRESS_OUT => fc_src_mac,
578 SRC_IP_ADDRESS_OUT => fc_src_ip,
579 SRC_UDP_PORT_OUT => fc_src_udp,
580
581
582 -- debug
583 DEBUG_OUT => open
584 );
585
586 -- Third stage: Frame Constructor
587 FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr
588 port map(
589 -- ports for user logic
590 RESET => RESET,
591 CLK => CLKSYS_IN,
b3e9a1b update
grzegorzkorcyl authored
592 LINK_OK_IN => '1', --link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
a53c7d0 first commit
grzegorzkorcyl authored
593 --
594 WR_EN_IN => fc_wr_en,
595 DATA_IN => fc_data,
596 START_OF_DATA_IN => fc_sod,
597 END_OF_DATA_IN => fc_eod,
598 IP_F_SIZE_IN => fc_ip_size,
599 UDP_P_SIZE_IN => fc_udp_size,
600 HEADERS_READY_OUT => fc_h_ready,
601 READY_OUT => fc_ready,
602 DEST_MAC_ADDRESS_IN => fc_dest_mac,
603 DEST_IP_ADDRESS_IN => fc_dest_ip,
604 DEST_UDP_PORT_IN => fc_dest_udp,
605 SRC_MAC_ADDRESS_IN => fc_src_mac,
606 SRC_IP_ADDRESS_IN => fc_src_ip,
607 SRC_UDP_PORT_IN => fc_src_udp,
608 FRAME_TYPE_IN => fc_type,
609 IHL_VERSION_IN => fc_ihl_version,
610 TOS_IN => fc_tos,
611 IDENTIFICATION_IN => fc_ident,
612 FLAGS_OFFSET_IN => fc_flags_offset,
613 TTL_IN => fc_ttl,
614 PROTOCOL_IN => fc_protocol,
4ba8a13 update
grzegorzkorcyl authored
615 FRAME_DELAY_IN => (others => '0'), -- gk 09.12.10
a53c7d0 first commit
grzegorzkorcyl authored
616 -- ports for packetTransmitter
617 RD_CLK => serdes_clk_125,
618 FT_DATA_OUT => ft_data,
619 FT_TX_EMPTY_OUT => ft_tx_empty,
b3e9a1b update
grzegorzkorcyl authored
620 FT_TX_RD_EN_IN => fc_test_rd_en, --mac_tx_read,
a53c7d0 first commit
grzegorzkorcyl authored
621 FT_START_OF_PACKET_OUT => ft_start_of_packet,
622 FT_TX_DONE_IN => mac_tx_done,
623 FT_TX_DISCFRM_IN => mac_tx_discfrm,
624 -- debug ports
625 BSM_CONSTR_OUT => open,
626 BSM_TRANS_OUT => open,
4ba8a13 update
grzegorzkorcyl authored
627 DEBUG_OUT => open
a53c7d0 first commit
grzegorzkorcyl authored
628 );
629
b3e9a1b update
grzegorzkorcyl authored
630 fc_test_rd_en <= '1' when g_SIMULATE = 1 and ft_tx_empty = '0' else mac_tx_read;
a53c7d0 first commit
grzegorzkorcyl authored
631
632
633 RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
634 port map(
635 CLK => CLKSYS_IN,
636 RESET => RESET,
637
638 -- signals to/from frame_receiver
639 RC_DATA_IN => fr_q,
640 FR_RD_EN_OUT => fr_rd_en,
641 FR_FRAME_VALID_IN => fr_frame_valid,
642 FR_GET_FRAME_OUT => fr_get_frame,
643 FR_FRAME_SIZE_IN => fr_frame_size,
644 FR_FRAME_PROTO_IN => fr_frame_proto,
645 FR_IP_PROTOCOL_IN => fr_ip_proto,
646
647 FR_SRC_MAC_ADDRESS_IN => fr_src_mac,
648 FR_DEST_MAC_ADDRESS_IN => fr_dest_mac,
649 FR_SRC_IP_ADDRESS_IN => fr_src_ip,
650 FR_DEST_IP_ADDRESS_IN => fr_dest_ip,
651 FR_SRC_UDP_PORT_IN => fr_src_udp,
652 FR_DEST_UDP_PORT_IN => fr_dest_udp,
653
654 -- signals to/from main controller
655 RC_RD_EN_IN => rc_rd_en,
656 RC_Q_OUT => rc_q,
657 RC_FRAME_WAITING_OUT => rc_frame_ready,
658 RC_LOADING_DONE_IN => rc_loading_done,
659 RC_FRAME_SIZE_OUT => rc_frame_size,
660 RC_FRAME_PROTO_OUT => rc_frame_proto,
661
662 RC_SRC_MAC_ADDRESS_OUT => rc_src_mac,
663 RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac,
664 RC_SRC_IP_ADDRESS_OUT => rc_src_ip,
665 RC_DEST_IP_ADDRESS_OUT => rc_dest_ip,
666 RC_SRC_UDP_PORT_OUT => rc_src_udp,
667 RC_DEST_UDP_PORT_OUT => rc_dest_udp,
668
669 -- statistics
670 FRAMES_RECEIVED_OUT => open,
671 BYTES_RECEIVED_OUT => open,
672
673
674 DEBUG_OUT => open
675 );
676
677
678 FRAME_TRANSMITTER: trb_net16_gbe_frame_trans
679 port map(
680 CLK => CLKSYS_IN,
681 RESET => RESET,
682 LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
683 TX_MAC_CLK => serdes_clk_125,
684 TX_EMPTY_IN => ft_tx_empty,
685 START_OF_PACKET_IN => ft_start_of_packet,
686 DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10
687
688 TX_FIFOAVAIL_OUT => mac_fifoavail,
689 TX_FIFOEOF_OUT => mac_fifoeof,
690 TX_FIFOEMPTY_OUT => mac_fifoempty,
691 TX_DONE_IN => mac_tx_done,
692 TX_STAT_EN_IN => mac_tx_staten,
693 TX_STATVEC_IN => mac_tx_statevec,
694 TX_DISCFRM_IN => mac_tx_discfrm,
695 -- Debug
696 BSM_INIT_OUT => open,
697 BSM_MAC_OUT => open,
698 BSM_TRANS_OUT => open,
699 DBG_RD_DONE_OUT => open,
700 DBG_INIT_DONE_OUT => open,
701 DBG_ENABLED_OUT => open,
702 DEBUG_OUT => open
703 );
704
705
706 FRAME_RECEIVER : trb_net16_gbe_frame_receiver
707 port map(
708 CLK => CLKSYS_IN,
709 RESET => RESET,
710 LINK_OK_IN => link_ok,
b3e9a1b update
grzegorzkorcyl authored
711 ALLOW_RX_IN => '1', --allow_rx,
a53c7d0 first commit
grzegorzkorcyl authored
712 RX_MAC_CLK => serdes_rx_clk,
713
714 -- input signals from TS_MAC
715 MAC_RX_EOF_IN => mac_rx_eof,
716 MAC_RX_ER_IN => mac_rx_er,
717 MAC_RXD_IN => mac_rxd,
718 MAC_RX_EN_IN => mac_rx_en,
719 MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err,
720 MAC_RX_FIFO_FULL_OUT => mac_rx_fifo_full,
721 MAC_RX_STAT_EN_IN => mac_rx_stat_en,
722 MAC_RX_STAT_VEC_IN => mac_rx_stat_vec,
723 -- output signal to control logic
724 FR_Q_OUT => fr_q,
725 FR_RD_EN_IN => fr_rd_en,
726 FR_FRAME_VALID_OUT => fr_frame_valid,
727 FR_GET_FRAME_IN => fr_get_frame,
728 FR_FRAME_SIZE_OUT => fr_frame_size,
729 FR_FRAME_PROTO_OUT => fr_frame_proto,
730 FR_IP_PROTOCOL_OUT => fr_ip_proto,
731 FR_ALLOWED_TYPES_IN => fr_allowed_types,
732 FR_ALLOWED_IP_IN => fr_allowed_ip,
733 FR_ALLOWED_UDP_IN => fr_allowed_udp,
734 FR_VLAN_ID_IN => vlan_id,
735
736 FR_SRC_MAC_ADDRESS_OUT => fr_src_mac,
737 FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac,
738 FR_SRC_IP_ADDRESS_OUT => fr_src_ip,
739 FR_DEST_IP_ADDRESS_OUT => fr_dest_ip,
740 FR_SRC_UDP_PORT_OUT => fr_src_udp,
741 FR_DEST_UDP_PORT_OUT => fr_dest_udp,
742
743 DEBUG_OUT => open
744 );
745
746
747
748 MAC: tsmac34
749 port map(
750 ----------------- clock and reset port declarations ------------------
751 hclk => CLKSYS_IN,
752 txmac_clk => serdes_clk_125,
753 rxmac_clk => serdes_rx_clk, --serdes_clk_125,
754 reset_n => GSR_N,
755 txmac_clk_en => mac_tx_clk_en,
756 rxmac_clk_en => mac_rx_clk_en,
757 ------------------- Input signals to the GMII ---------------- NOT USED
ac8e2d5 update
grzegorzkorcyl authored
758 rxd => pcs_rxd_qq,
759 rx_dv => pcs_rx_en_qq,
760 rx_er => pcs_rx_er_qq,
a53c7d0 first commit
grzegorzkorcyl authored
761 col => mac_col,
762 crs => mac_crs,
763 -------------------- Input signals to the CPU I/F -------------------
764 haddr => mac_haddr,
765 hdatain => mac_hdataout,
766 hcs_n => mac_hcs,
767 hwrite_n => mac_hwrite,
768 hread_n => mac_hread,
769 ---------------- Input signals to the Tx MAC FIFO I/F ---------------
770 tx_fifodata => ft_data(7 downto 0),
771 tx_fifoavail => mac_fifoavail,
772 tx_fifoeof => mac_fifoeof,
773 tx_fifoempty => mac_fifoempty,
774 tx_sndpaustim => x"0000",
775 tx_sndpausreq => '0',
776 tx_fifoctrl => '0', -- always data frame
777 ---------------- Input signals to the Rx MAC FIFO I/F ---------------
ac8e2d5 update
grzegorzkorcyl authored
778 rx_fifo_full => mac_rx_fifo_full,
a53c7d0 first commit
grzegorzkorcyl authored
779 ignore_pkt => '0',
780 ---------------- Output signals from the GMII -----------------------
781 txd => pcs_txd,
782 tx_en => pcs_tx_en,
783 tx_er => pcs_tx_er,
784 ----------------- Output signals from the CPU I/F -------------------
785 hdataout => open,
786 hdataout_en_n => mac_hdata_en,
787 hready_n => mac_hready,
788 cpu_if_gbit_en => tsmac_gbit_en,
789 ------------- Output signals from the Tx MAC FIFO I/F ---------------
790 tx_macread => mac_tx_read,
791 tx_discfrm => mac_tx_discfrm,
792 tx_staten => mac_tx_staten, -- gk 08.06.10
793 tx_statvec => mac_tx_statevec, -- gk 08.06.10
794 tx_done => mac_tx_done,
795 ------------- Output signals from the Rx MAC FIFO I/F ---------------
796 rx_fifo_error => mac_rx_fifo_err, --open,
797 rx_stat_vector => mac_rx_stat_vec, --open,
b3e9a1b update
grzegorzkorcyl authored
798 rx_dbout => open, --mac_rxd, --open,
799 rx_write => open, --mac_rx_en, --open,
a53c7d0 first commit
grzegorzkorcyl authored
800 rx_stat_en => mac_rx_stat_en, --open,
b3e9a1b update
grzegorzkorcyl authored
801 rx_eof => open, --mac_rx_eof, --open,
a53c7d0 first commit
grzegorzkorcyl authored
802 rx_error => mac_rx_er --open
803 );
804
b3e9a1b update
grzegorzkorcyl authored
805 -- LOOPBACK FOR TESTBENCH
806 mac_rxd <= ft_data(7 downto 0);
807 mac_rx_en <= fc_test_rd_en;-- mac_fifoavail;
808 mac_rx_eof <= mac_fifoeof;
809
a53c7d0 first commit
grzegorzkorcyl authored
810 SYNC_GMII_RX_PROC : process(serdes_rx_clk)
811 begin
812 if rising_edge(serdes_rx_clk) then
813 pcs_rxd_q <= pcs_rxd;
814 pcs_rx_en_q <= pcs_rx_en;
815 pcs_rx_er_q <= pcs_rx_er;
816
817 pcs_rxd_qq <= pcs_rxd_q;
818 pcs_rx_en_qq <= pcs_rx_en_q;
819 pcs_rx_er_qq <= pcs_rx_er_q;
820 end if;
821 end process SYNC_GMII_RX_PROC;
822
823 SYNC_GMII_TX_PROC : process(serdes_clk_125)
824 begin
825 if rising_edge(serdes_clk_125) then
826 pcs_txd_q <= pcs_txd;
827 pcs_tx_en_q <= pcs_tx_en;
828 pcs_tx_er_q <= pcs_tx_er;
829
830 pcs_txd_qq <= pcs_txd_q;
831 pcs_tx_en_qq <= pcs_tx_en_q;
832 pcs_tx_er_qq <= pcs_tx_er_q;
833 end if;
834 end process SYNC_GMII_TX_PROC;
835
836 PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b
837 generic map(
838 USE_125MHZ_EXTCLK => 0
839 )
840 port map(
841 RESET => RESET,
842 GSR_N => GSR_N,
843 CLK_125_OUT => serdes_clk_125,
ac8e2d5 update
grzegorzkorcyl authored
844 CLK_125_RX_OUT => serdes_rx_clk, --open,
a53c7d0 first commit
grzegorzkorcyl authored
845 CLK_125_IN => CLKGBE_IN,
ac8e2d5 update
grzegorzkorcyl authored
846 FT_TX_CLK_EN_OUT => mac_tx_clk_en,
847 FT_RX_CLK_EN_OUT => mac_rx_clk_en,
a53c7d0 first commit
grzegorzkorcyl authored
848 --connection to frame transmitter (tsmac)
849 FT_COL_OUT => mac_col,
850 FT_CRS_OUT => mac_crs,
851 FT_TXD_IN => pcs_txd_qq,
852 FT_TX_EN_IN => pcs_tx_en_qq,
853 FT_TX_ER_IN => pcs_tx_er_qq,
854 FT_RXD_OUT => pcs_rxd,
ac8e2d5 update
grzegorzkorcyl authored
855 FT_RX_EN_OUT => pcs_rx_en,
856 FT_RX_ER_OUT => pcs_rx_er,
e88e265 update
grzegorzkorcyl authored
857
a53c7d0 first commit
grzegorzkorcyl authored
858 -- Autonegotiation stuff
859 MR_ADV_ABILITY_IN => x"0020", -- full duplex only
ac8e2d5 update
grzegorzkorcyl authored
860 MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability,
a53c7d0 first commit
grzegorzkorcyl authored
861 MR_AN_PAGE_RX_OUT => pcs_an_page_rx,
862 MR_AN_COMPLETE_OUT => pcs_an_complete,
ac8e2d5 update
grzegorzkorcyl authored
863 MR_RESET_IN => RESET,
864 MR_MODE_IN => '0', --MR_MODE_IN,
a53c7d0 first commit
grzegorzkorcyl authored
865 MR_AN_ENABLE_IN => '1', -- do autonegotiation
866 MR_RESTART_AN_IN => '0', --MR_RESTART_IN,
e88e265 update
grzegorzkorcyl authored
867
868 SD_RX_CLK_IN => SD_RX_CLK_IN,
869 SD_TX_DATA_OUT => SD_TX_DATA_OUT,
870 SD_TX_KCNTL_OUT => SD_TX_KCNTL_OUT,
871 SD_TX_CORRECT_DISP_OUT => SD_TX_CORRECT_DISP_OUT,
872 SD_RX_DATA_IN => SD_RX_DATA_IN,
873 SD_RX_KCNTL_IN => SD_RX_KCNTL_IN,
874 SD_RX_DISP_ERROR_IN => SD_RX_DISP_ERROR_IN,
875 SD_RX_CV_ERROR_IN => SD_RX_CV_ERROR_IN,
876 SD_RX_SERDES_RST_OUT => SD_RX_SERDES_RST_OUT,
877 SD_RX_PCS_RST_OUT => SD_RX_PCS_RST_OUT,
878 SD_TX_PCS_RST_OUT => SD_TX_PCS_RST_OUT,
879 SD_RX_LOS_IN => SD_RX_LOS_IN,
880 SD_SIGNAL_DETECTED_IN => SD_SIGNAL_DETECTED_IN,
881 SD_RX_CDR_IN => SD_RX_CDR_IN,
882 SD_TX_PLL_LOL_IN => SD_TX_PLL_LOL_IN,
5e3450e update
grzegorzkorcyl authored
883 SD_QUAD_RST_OUT => SD_QUAD_RST_OUT,
884 SD_XMIT_OUT => SD_XMIT_OUT
a53c7d0 first commit
grzegorzkorcyl authored
885 );
886
887
888 -- FrameConstructor fixed magic values
889 --fc_type <= x"0008";
890 fc_ihl_version <= x"45";
891 fc_tos <= x"10";
892
893 -- FrameConstructor fixed magic values
894 --fc_type <= x"0008";
895 fc_ihl_version <= x"45";
896 fc_tos <= x"10";
18c5bab update
grzegorzkorcyl authored
897
898 LINK_OK_OUT <= link_ok;
a53c7d0 first commit
grzegorzkorcyl authored
899
900 end architecture CNTester_module;
Something went wrong with that request. Please try again.