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a53c7d0 first commit
grzegorzkorcyl authored Feb 29, 2012
1 LIBRARY ieee;
2 use ieee.std_logic_1164.all;
3 USE IEEE.numeric_std.ALL;
4 USE IEEE.std_logic_UNSIGNED.ALL;
5 use IEEE.std_logic_arith.all;
6
7 library work;
8 use work.trb_net_std.all;
9 use work.trb_net_components.all;
10 use work.trb_net16_hub_func.all;
11
12 use work.trb_net_gbe_components.all;
13 use work.trb_net_gbe_protocols.all;
14
15 entity CNTester_module is
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16 generic ( g_GENERATE_STAT : integer range 0 to 1 := 0);
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17 port (
18 CLKSYS_IN : in std_logic;
19 CLKGBE_IN : in std_logic;
20 RESET : in std_logic;
21 GSR_N : in std_logic;
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22 LINK_OK_OUT : out std_logic;
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23
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24 MAC_ADDR_IN : in std_logic_vector(47 downto 0);
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25 TIMESTAMP_IN : in std_logic_vector(31 downto 0);
26 DEST_ADDR_IN : in std_logic_vector(15 downto 0);
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27 GENERATE_PACKET_IN : in std_logic;
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28 SIZE_IN : in std_logic_vector(15 downto 0);
29 BUSY_OUT : out std_logic;
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30
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31 MODULE_SELECT_OUT : out std_logic_vector(7 downto 0);
32 MODULE_RD_EN_OUT : out std_logic;
33 MODULE_DATA_IN : in std_logic_vector(71 downto 0);
34 STOP_TRANSMISSION_OUT : out std_logic;
35 START_STAT_IN : in std_logic;
36
37 MODULE_DATA_OUT : out std_logic_vector(71 downto 0);
38 MODULE_RD_EN_IN : in std_logic;
39 MODULE_SELECTED_IN : in std_logic;
40 MODULE_FULL_OUT : out std_logic;
41
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42 TEST_PORT_IN : in std_logic_vector(123 downto 0);
43 TEST_PORT_OUT : out std_logic_vector(123 downto 0);
44
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45 -- serdes io
46 SD_RX_CLK_IN : in std_logic;
47 SD_TX_DATA_OUT : out std_logic_vector(7 downto 0);
48 SD_TX_KCNTL_OUT : out std_logic;
49 SD_TX_CORRECT_DISP_OUT : out std_logic;
50 SD_RX_DATA_IN : in std_logic_vector(7 downto 0);
51 SD_RX_KCNTL_IN : in std_logic;
52 SD_RX_DISP_ERROR_IN : in std_logic;
53 SD_RX_CV_ERROR_IN : in std_logic;
54 SD_RX_SERDES_RST_OUT : out std_logic;
55 SD_RX_PCS_RST_OUT : out std_logic;
56 SD_TX_PCS_RST_OUT : out std_logic;
57 SD_RX_LOS_IN : in std_logic;
58 SD_SIGNAL_DETECTED_IN : in std_logic;
59 SD_RX_CDR_IN : in std_logic;
60 SD_TX_PLL_LOL_IN : in std_logic;
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61 SD_QUAD_RST_OUT : out std_logic;
62 SD_XMIT_OUT : out std_logic
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63 );
64 end entity CNTester_module;
65
66 architecture CNTester_module of CNTester_module is
67
68
69 component tsmac34
70 port(
71 --------------- clock and reset port declarations ------------------
72 hclk : in std_logic;
73 txmac_clk : in std_logic;
74 rxmac_clk : in std_logic;
75 reset_n : in std_logic;
76 txmac_clk_en : in std_logic;
77 rxmac_clk_en : in std_logic;
78 ------------------- Input signals to the GMII ----------------
79 rxd : in std_logic_vector(7 downto 0);
80 rx_dv : in std_logic;
81 rx_er : in std_logic;
82 col : in std_logic;
83 crs : in std_logic;
84 -------------------- Input signals to the CPU I/F -------------------
85 haddr : in std_logic_vector(7 downto 0);
86 hdatain : in std_logic_vector(7 downto 0);
87 hcs_n : in std_logic;
88 hwrite_n : in std_logic;
89 hread_n : in std_logic;
90 ---------------- Input signals to the Tx MAC FIFO I/F ---------------
91 tx_fifodata : in std_logic_vector(7 downto 0);
92 tx_fifoavail : in std_logic;
93 tx_fifoeof : in std_logic;
94 tx_fifoempty : in std_logic;
95 tx_sndpaustim : in std_logic_vector(15 downto 0);
96 tx_sndpausreq : in std_logic;
97 tx_fifoctrl : in std_logic;
98 ---------------- Input signals to the Rx MAC FIFO I/F ---------------
99 rx_fifo_full : in std_logic;
100 ignore_pkt : in std_logic;
101 -------------------- Output signals from the GMII -----------------------
102 txd : out std_logic_vector(7 downto 0);
103 tx_en : out std_logic;
104 tx_er : out std_logic;
105 -------------------- Output signals from the CPU I/F -------------------
106 hdataout : out std_logic_vector(7 downto 0);
107 hdataout_en_n : out std_logic;
108 hready_n : out std_logic;
109 cpu_if_gbit_en : out std_logic;
110 ---------------- Output signals from the Tx MAC FIFO I/F ---------------
111 tx_macread : out std_logic;
112 tx_discfrm : out std_logic;
113 tx_staten : out std_logic;
114 tx_done : out std_logic;
115 tx_statvec : out std_logic_vector(30 downto 0);
116 ---------------- Output signals from the Rx MAC FIFO I/F ---------------
117 rx_fifo_error : out std_logic;
118 rx_stat_vector : out std_logic_vector(31 downto 0);
119 rx_dbout : out std_logic_vector(7 downto 0);
120 rx_write : out std_logic;
121 rx_stat_en : out std_logic;
122 rx_eof : out std_logic;
123 rx_error : out std_logic
124 );
125 end component;
126
127 --*********
128 -- MOST OF THE SIGNAL ARE NOT NEEDED, JUST COPIED FROM THE ORIGINAL BUF
129
130 signal pc_wr_en : std_logic;
131 signal pc_data : std_logic_vector(7 downto 0);
132 signal pc_eod : std_logic;
133 signal pc_sos : std_logic;
134 signal pc_ready : std_logic;
135 signal pc_padding : std_logic;
136 signal pc_decoding : std_logic_vector(31 downto 0);
137 signal pc_event_id : std_logic_vector(31 downto 0);
138 signal pc_queue_dec : std_logic_vector(31 downto 0);
139 signal pc_max_frame_size : std_logic_vector(15 downto 0);
140 signal pc_bsm_constr : std_logic_vector(3 downto 0);
141 signal pc_bsm_load : std_logic_vector(3 downto 0);
142 signal pc_bsm_save : std_logic_vector(3 downto 0);
143 signal pc_shf_empty : std_logic;
144 signal pc_shf_full : std_logic;
145 signal pc_shf_wr_en : std_logic;
146 signal pc_shf_rd_en : std_logic;
147 signal pc_shf_q : std_logic_vector(7 downto 0);
148 signal pc_df_empty : std_logic;
149 signal pc_df_full : std_logic;
150 signal pc_df_wr_en : std_logic;
151 signal pc_df_rd_en : std_logic;
152 signal pc_df_q : std_logic_vector(7 downto 0);
153 signal pc_all_ctr : std_logic_vector(4 downto 0);
154 signal pc_sub_ctr : std_logic_vector(4 downto 0);
155 signal pc_bytes_loaded : std_logic_vector(15 downto 0);
156 signal pc_size_left : std_logic_vector(31 downto 0);
157 signal pc_sub_size_to_save : std_logic_vector(31 downto 0);
158 signal pc_sub_size_loaded : std_logic_vector(31 downto 0);
159 signal pc_sub_bytes_loaded : std_logic_vector(31 downto 0);
160 signal pc_queue_size : std_logic_vector(31 downto 0);
161 signal pc_act_queue_size : std_logic_vector(31 downto 0);
162
163 signal fee_read : std_logic;
164 signal cts_readout_finished : std_logic;
165 signal cts_dataready : std_logic;
166 signal cts_length : std_logic_vector(15 downto 0);
167 signal cts_data : std_logic_vector(31 downto 0); -- DHDR of rest packet
168 signal cts_error_pattern : std_logic_vector(31 downto 0);
169
170 signal pc_sub_size : std_logic_vector(31 downto 0);
171 signal pc_trig_nr : std_logic_vector(31 downto 0);
172
173 signal tc_wr_en : std_logic;
174 signal tc_data : std_logic_vector(7 downto 0);
175 signal tc_ip_size : std_logic_vector(15 downto 0);
176 signal tc_udp_size : std_logic_vector(15 downto 0);
177 signal tc_ident : std_logic_vector(15 downto 0);
178 signal tc_flags_offset : std_logic_vector(15 downto 0);
179 signal tc_sod : std_logic;
180 signal tc_eod : std_logic;
181 signal tc_h_ready : std_logic;
182 signal tc_ready : std_logic;
183 signal fc_dest_mac : std_logic_vector(47 downto 0);
184 signal fc_dest_ip : std_logic_vector(31 downto 0);
185 signal fc_dest_udp : std_logic_vector(15 downto 0);
186 signal fc_src_mac : std_logic_vector(47 downto 0);
187 signal fc_src_ip : std_logic_vector(31 downto 0);
188 signal fc_src_udp : std_logic_vector(15 downto 0);
189 signal fc_type : std_logic_vector(15 downto 0);
190 signal fc_ihl_version : std_logic_vector(7 downto 0);
191 signal fc_tos : std_logic_vector(7 downto 0);
192 signal fc_ttl : std_logic_vector(7 downto 0);
193 signal fc_protocol : std_logic_vector(7 downto 0);
194 signal fc_bsm_constr : std_logic_vector(7 downto 0);
195 signal fc_bsm_trans : std_logic_vector(3 downto 0);
196
197 signal ft_data : std_logic_vector(8 downto 0);-- gk 04.05.10
198 signal ft_tx_empty : std_logic;
199 signal ft_start_of_packet : std_logic;
200 signal ft_bsm_init : std_logic_vector(3 downto 0);
201 signal ft_bsm_mac : std_logic_vector(3 downto 0);
202 signal ft_bsm_trans : std_logic_vector(3 downto 0);
203
204 signal mac_haddr : std_logic_vector(7 downto 0);
205 signal mac_hdataout : std_logic_vector(7 downto 0);
206 signal mac_hcs : std_logic;
207 signal mac_hwrite : std_logic;
208 signal mac_hread : std_logic;
209 signal mac_fifoavail : std_logic;
210 signal mac_fifoempty : std_logic;
211 signal mac_fifoeof : std_logic;
212 signal mac_hready : std_logic;
213 signal mac_hdata_en : std_logic;
214 signal mac_tx_done : std_logic;
215 signal mac_tx_read : std_logic;
216
217 signal serdes_clk_125 : std_logic;
218 signal mac_tx_clk_en : std_logic;
219 signal mac_rx_clk_en : std_logic;
220 signal mac_col : std_logic;
221 signal mac_crs : std_logic;
222 signal pcs_txd : std_logic_vector(7 downto 0);
223 signal pcs_tx_en : std_logic;
224 signal pcs_tx_er : std_logic;
225 signal pcs_an_lp_ability : std_logic_vector(15 downto 0);
226 signal pcs_an_complete : std_logic;
227 signal pcs_an_page_rx : std_logic;
228
229 signal pcs_stat_debug : std_logic_vector(63 downto 0);
230
231 signal stage_stat_regs : std_logic_vector(31 downto 0);
232 signal stage_ctrl_regs : std_logic_vector(31 downto 0);
233
234 signal analyzer_debug : std_logic_vector(63 downto 0);
235
236 signal ip_cfg_start : std_logic;
237 signal ip_cfg_bank : std_logic_vector(3 downto 0);
238 signal ip_cfg_done : std_logic;
239
240 signal ip_cfg_mem_addr : std_logic_vector(7 downto 0);
241 signal ip_cfg_mem_data : std_logic_vector(31 downto 0);
242 signal ip_cfg_mem_clk : std_logic;
243
244 -- gk 22.04.10
245 signal max_packet : std_logic_vector(31 downto 0);
246 signal min_packet : std_logic_vector(31 downto 0);
247 signal use_gbe : std_logic;
248 signal use_trbnet : std_logic;
249 signal use_multievents : std_logic;
250 -- gk 26.04.10
251 signal readout_ctr : std_logic_vector(23 downto 0);
252 signal readout_ctr_valid : std_logic;
253 signal gbe_trig_nr : std_logic_vector(31 downto 0);
254 -- gk 28.04.10
255 signal pc_delay : std_logic_vector(31 downto 0);
256 -- gk 04.05.10
257 signal ft_eod : std_logic;
258 -- gk 08.06.10
259 signal mac_tx_staten : std_logic;
260 signal mac_tx_statevec : std_logic_vector(30 downto 0);
261 signal mac_tx_discfrm : std_logic;
262
263 -- gk 21.07.10
264 signal allow_large : std_logic;
265
266 -- gk 28.07.10
267 signal bytes_sent_ctr : std_logic_vector(31 downto 0);
268 signal monitor_sent : std_logic_vector(31 downto 0);
269 signal monitor_dropped : std_logic_vector(31 downto 0);
270 signal monitor_sm : std_logic_vector(31 downto 0);
271 signal monitor_lr : std_logic_vector(31 downto 0);
272 signal monitor_hr : std_logic_vector(31 downto 0);
273 signal monitor_fifos : std_logic_vector(31 downto 0);
274 signal monitor_fifos_q : std_logic_vector(31 downto 0);
275 signal monitor_discfrm : std_logic_vector(31 downto 0);
276
277 -- gk 02.08.10
278 signal discfrm_ctr : std_logic_vector(31 downto 0);
279
280 -- gk 30.09.10
281 signal fc_rd_en : std_logic;
282 signal link_ok : std_logic;
283 signal link_ok_timeout_ctr : std_logic_vector(15 downto 0);
284
285 type linkStates is (ACTIVE, INACTIVE, TIMEOUT, FINALIZE);
286 signal link_current_state, link_next_state : linkStates;
287
288 signal link_down_ctr : std_logic_vector(15 downto 0);
289 signal link_down_ctr_lock : std_logic;
290
291 signal link_state : std_logic_vector(3 downto 0);
292
293 signal monitor_empty : std_logic_vector(31 downto 0);
294
295 -- gk 07.10.10
296 signal pc_eos : std_logic;
297
298 -- gk 09.12.10
299 signal frame_delay : std_logic_vector(31 downto 0);
300
301 -- gk 13.02.11
302 signal pcs_rxd : std_logic_vector(7 downto 0);
303 signal pcs_rx_en : std_logic;
304 signal pcs_rx_er : std_logic;
305 signal mac_rx_eof : std_logic;
306 signal mac_rx_er : std_logic;
307 signal mac_rxd : std_logic_vector(7 downto 0);
308 signal mac_rx_fifo_err : std_logic;
309 signal mac_rx_fifo_full : std_logic;
310 signal mac_rx_en : std_logic;
311 signal mac_rx_stat_en : std_logic;
312 signal mac_rx_stat_vec : std_logic_vector(31 downto 0);
313 signal fr_q : std_logic_vector(8 downto 0);
314 signal fr_rd_en : std_logic;
315 signal fr_frame_valid : std_logic;
316 signal rc_rd_en : std_logic;
317 signal rc_q : std_logic_vector(8 downto 0);
318 signal rc_frames_rec_ctr : std_logic_vector(31 downto 0);
319 signal tc_pc_ready : std_logic;
320 signal tc_pc_h_ready : std_logic;
321 signal mc_ctrl_frame_req : std_logic;
322 signal mc_data : std_logic_vector(8 downto 0);
323 signal mc_rd_en : std_logic;
324 signal fc_wr_en : std_logic;
325 signal fc_data : std_logic_vector(7 downto 0);
326 signal fc_ip_size : std_logic_vector(15 downto 0);
327 signal fc_udp_size : std_logic_vector(15 downto 0);
328 signal fc_ident : std_logic_vector(15 downto 0);
329 signal fc_flags_offset : std_logic_vector(15 downto 0);
330 signal fc_sod : std_logic;
331 signal fc_eod : std_logic;
332 signal fc_h_ready : std_logic;
333 signal fc_ready : std_logic;
334 signal rc_frame_ready : std_logic;
335 signal allow_rx : std_logic;
336 signal fr_frame_size : std_logic_vector(15 downto 0);
337 signal rc_frame_size : std_logic_vector(15 downto 0);
338 signal mc_frame_size : std_logic_vector(15 downto 0);
339 signal ic_dest_mac : std_logic_vector(47 downto 0);
340 signal ic_dest_ip : std_logic_vector(31 downto 0);
341 signal ic_dest_udp : std_logic_vector(15 downto 0);
342 signal ic_src_mac : std_logic_vector(47 downto 0);
343 signal ic_src_ip : std_logic_vector(31 downto 0);
344 signal ic_src_udp : std_logic_vector(15 downto 0);
345 signal pc_transmit_on : std_logic;
346 signal rc_bytes_rec : std_logic_vector(31 downto 0);
347 signal rc_debug : std_logic_vector(63 downto 0);
348 signal mc_busy : std_logic;
349 signal tsmac_gbit_en : std_logic;
350 signal mc_transmit_ctrl : std_logic;
351 signal mc_transmit_data : std_logic;
352 signal rc_loading_done : std_logic;
353 signal fr_get_frame : std_logic;
354 signal mc_transmit_done : std_logic;
355
356 signal dbg_fr : std_logic_vector(95 downto 0);
357 signal dbg_rc : std_logic_vector(63 downto 0);
358 signal dbg_mc : std_logic_vector(63 downto 0);
359 signal dbg_tc : std_logic_vector(63 downto 0);
360
361 signal fr_allowed_types : std_logic_vector(31 downto 0);
362 signal fr_allowed_ip : std_logic_vector(31 downto 0);
363 signal fr_allowed_udp : std_logic_vector(31 downto 0);
364
365 signal fr_frame_proto : std_logic_vector(15 downto 0);
366 signal rc_frame_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
367
368 signal dbg_select_rec : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
369 signal dbg_select_sent : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
370 signal dbg_select_protos : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
371
372 signal serdes_rx_clk : std_logic;
373
374 signal vlan_id : std_logic_vector(31 downto 0);
375 signal mc_type : std_logic_vector(15 downto 0);
376 signal fr_src_mac : std_logic_vector(47 downto 0);
377 signal fr_dest_mac : std_logic_vector(47 downto 0);
378 signal fr_src_ip : std_logic_vector(31 downto 0);
379 signal fr_dest_ip : std_logic_vector(31 downto 0);
380 signal fr_src_udp : std_logic_vector(15 downto 0);
381 signal fr_dest_udp : std_logic_vector(15 downto 0);
382 signal rc_src_mac : std_logic_vector(47 downto 0);
383 signal rc_dest_mac : std_logic_vector(47 downto 0);
384 signal rc_src_ip : std_logic_vector(31 downto 0);
385 signal rc_dest_ip : std_logic_vector(31 downto 0);
386 signal rc_src_udp : std_logic_vector(15 downto 0);
387 signal rc_dest_udp : std_logic_vector(15 downto 0);
388
389 signal mc_dest_mac : std_logic_vector(47 downto 0);
390 signal mc_dest_ip : std_logic_vector(31 downto 0);
391 signal mc_dest_udp : std_logic_vector(15 downto 0);
392 signal mc_src_mac : std_logic_vector(47 downto 0);
393 signal mc_src_ip : std_logic_vector(31 downto 0);
394 signal mc_src_udp : std_logic_vector(15 downto 0);
395
396 signal dbg_ft : std_logic_vector(63 downto 0);
397
398 signal fr_ip_proto : std_logic_vector(7 downto 0);
399 signal mc_ip_proto : std_logic_vector(7 downto 0);
400
401 attribute syn_preserve : boolean;
402 attribute syn_keep : boolean;
403 attribute syn_keep of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true;
404 attribute syn_preserve of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true;
405
406 signal pcs_txd_q, pcs_rxd_q : std_logic_vector(7 downto 0);
407 signal pcs_tx_en_q, pcs_tx_er_q, pcs_rx_en_q, pcs_rx_er_q, mac_col_q, mac_crs_q : std_logic;
408
409 signal pcs_txd_qq, pcs_rxd_qq : std_logic_vector(7 downto 0);
410 signal pcs_tx_en_qq, pcs_tx_er_qq, pcs_rx_en_qq, pcs_rx_er_qq, mac_col_qq, mac_crs_qq : std_logic;
411
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412 signal fc_test_rd_en, fc_test_rd_en_q : std_logic;
413 signal fr_rx_clk : std_logic;
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414 signal serdes_rx_clk_a, serdes_clk_125_a : std_logic;
415
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416 begin
417
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418 -- WARNING: setting allowed types to constat true
419 fr_allowed_types <= x"0000_00ff"; -- only test protocol allowed
420 fr_allowed_ip <= x"0000_00ff";
421 fr_allowed_udp <= x"0000_00ff";
422 vlan_id <= (others => '0');
423
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424 MAIN_CONTROL : trb_net16_gbe_main_control
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425 generic map ( g_GENERATE_STAT => g_GENERATE_STAT)
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426 port map(
427 CLK => CLKSYS_IN,
428 CLK_125 => CLKGBE_IN,
429 RESET => RESET,
430
431 MC_LINK_OK_OUT => link_ok,
432 MC_RESET_LINK_IN => '0',
433
434 -- signals to/from receive controller
435 RC_FRAME_WAITING_IN => rc_frame_ready,
436 RC_LOADING_DONE_OUT => rc_loading_done,
437 RC_DATA_IN => rc_q,
438 RC_RD_EN_OUT => rc_rd_en,
439 RC_FRAME_SIZE_IN => rc_frame_size,
440 RC_FRAME_PROTO_IN => rc_frame_proto,
441
442 RC_SRC_MAC_ADDRESS_IN => rc_src_mac,
443 RC_DEST_MAC_ADDRESS_IN => rc_dest_mac,
444 RC_SRC_IP_ADDRESS_IN => rc_src_ip,
445 RC_DEST_IP_ADDRESS_IN => rc_dest_ip,
446 RC_SRC_UDP_PORT_IN => rc_src_udp,
447 RC_DEST_UDP_PORT_IN => rc_dest_udp,
448
449 -- signals to/from transmit controller
450 TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl,
451 TC_TRANSMIT_DATA_OUT => mc_transmit_data,
452 TC_DATA_OUT => mc_data,
453 TC_RD_EN_IN => mc_rd_en,
454 TC_FRAME_SIZE_OUT => mc_frame_size,
455 TC_FRAME_TYPE_OUT => mc_type,
456 TC_IP_PROTOCOL_OUT => mc_ip_proto,
457
458 TC_DEST_MAC_OUT => mc_dest_mac,
459 TC_DEST_IP_OUT => mc_dest_ip,
460 TC_DEST_UDP_OUT => mc_dest_udp,
461 TC_SRC_MAC_OUT => mc_src_mac,
462 TC_SRC_IP_OUT => mc_src_ip,
463 TC_SRC_UDP_OUT => mc_src_udp,
464
465 TC_BUSY_IN => mc_busy,
466 TC_TRANSMIT_DONE_IN => mc_transmit_done,
467
468 -- signals to/from packet constructor
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469 PC_READY_IN => '1',
470 PC_TRANSMIT_ON_IN => '0',
471 PC_SOD_IN => '0',
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472
473 -- signals to/from sgmii/gbe pcs_an_complete
474 PCS_AN_COMPLETE_IN => pcs_an_complete,
475
476 -- signals to/from hub
477 MC_UNIQUE_ID_IN => (others => '0'),
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478
479 CNT_GENERATE_PACKET_IN => GENERATE_PACKET_IN,
480 CNT_TIMESTAMP_IN => TIMESTAMP_IN,
481 CNT_DEST_ADDR_IN => DEST_ADDR_IN,
482 CNT_SIZE_IN => SIZE_IN,
483 CNT_BUSY_OUT => BUSY_OUT,
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484
485 CNT_MODULE_SELECT_OUT => MODULE_SELECT_OUT,
486 CNT_MODULE_RD_EN_OUT => MODULE_RD_EN_OUT,
487 CNT_MODULE_DATA_IN => MODULE_DATA_IN,
488 CNT_STOP_TRANSMISSION_OUT => STOP_TRANSMISSION_OUT,
489 CNT_START_STAT_IN => START_STAT_IN,
490
491 CNT_MODULE_DATA_OUT => MODULE_DATA_OUT,
492 CNT_MODULE_RD_EN_IN => MODULE_RD_EN_IN,
493 CNT_MODULE_SELECTED_IN => MODULE_SELECTED_IN,
494 CNT_MODULE_FULL_OUT => MODULE_FULL_OUT,
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495 CNT_MODULE_ID_IN => MAC_ADDR_IN(3 downto 0),
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496
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497 GSC_CLK_IN => '0',
498 GSC_INIT_DATAREADY_OUT => open,
499 GSC_INIT_DATA_OUT => open,
500 GSC_INIT_PACKET_NUM_OUT => open,
501 GSC_INIT_READ_IN => '0',
502 GSC_REPLY_DATAREADY_IN => '0',
503 GSC_REPLY_DATA_IN => (others => '0'),
504 GSC_REPLY_PACKET_NUM_IN => (others => '0'),
505 GSC_REPLY_READ_OUT => open,
506 GSC_BUSY_IN => '0',
507
508 -- signal to/from Host interface of TriSpeed MAC
509 TSM_HADDR_OUT => mac_haddr,
510 TSM_HDATA_OUT => mac_hdataout,
511 TSM_HCS_N_OUT => mac_hcs,
512 TSM_HWRITE_N_OUT => mac_hwrite,
513 TSM_HREAD_N_OUT => mac_hread,
514 TSM_HREADY_N_IN => mac_hready,
515 TSM_HDATA_EN_N_IN => mac_hdata_en,
516 TSM_RX_STAT_VEC_IN => mac_rx_stat_vec,
517 TSM_RX_STAT_EN_IN => mac_rx_stat_en,
518
519 SELECT_REC_FRAMES_OUT => open,
520 SELECT_SENT_FRAMES_OUT => open,
521 SELECT_PROTOS_DEBUG_OUT => open,
522
523 DEBUG_OUT => open
524 );
525
526
527 TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control
528 port map(
529 CLK => CLKSYS_IN,
530 RESET => RESET,
531
532 -- signals to/from packet constructor
533 PC_READY_IN => pc_ready,
534 PC_DATA_IN => tc_data,
535 PC_WR_EN_IN => tc_wr_en,
536 PC_IP_SIZE_IN => tc_ip_size,
537 PC_UDP_SIZE_IN => tc_udp_size,
538 PC_FLAGS_OFFSET_IN => tc_flags_offset,
539 PC_SOD_IN => tc_sod,
540 PC_EOD_IN => tc_eod,
541 PC_FC_READY_OUT => tc_pc_ready,
542 PC_FC_H_READY_OUT => tc_pc_h_ready,
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543 PC_TRANSMIT_ON_IN => '0',
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544
545 -- signals from ip_configurator used by packet constructor
546 IC_DEST_MAC_ADDRESS_IN => ic_dest_mac,
547 IC_DEST_IP_ADDRESS_IN => ic_dest_ip,
548 IC_DEST_UDP_PORT_IN => ic_dest_udp,
549 IC_SRC_MAC_ADDRESS_IN => ic_src_mac,
550 IC_SRC_IP_ADDRESS_IN => ic_src_ip,
551 IC_SRC_UDP_PORT_IN => ic_src_udp,
552
553 -- signal to/from main controller
554 MC_TRANSMIT_CTRL_IN => mc_transmit_ctrl,
555 MC_TRANSMIT_DATA_IN => mc_transmit_data,
556 MC_DATA_IN => mc_data,
557 MC_RD_EN_OUT => mc_rd_en,
558 MC_FRAME_SIZE_IN => mc_frame_size,
559 MC_FRAME_TYPE_IN => mc_type,
560 MC_IP_PROTOCOL_IN => mc_ip_proto,
561
562 MC_DEST_MAC_IN => mc_dest_mac,
563 MC_DEST_IP_IN => mc_dest_ip,
564 MC_DEST_UDP_IN => mc_dest_udp,
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565 MC_SRC_MAC_IN => MAC_ADDR_IN, --mc_src_mac, to identify the module
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566 MC_SRC_IP_IN => mc_src_ip,
567 MC_SRC_UDP_IN => mc_src_udp,
568
569 MC_BUSY_OUT => mc_busy,
570 MC_TRANSMIT_DONE_OUT => mc_transmit_done,
571
572 -- signal to/from frame constructor
573 FC_DATA_OUT => fc_data,
574 FC_WR_EN_OUT => fc_wr_en,
575 FC_READY_IN => fc_ready,
576 FC_H_READY_IN => fc_h_ready,
577 FC_FRAME_TYPE_OUT => fc_type,
578 FC_IP_SIZE_OUT => fc_ip_size,
579 FC_UDP_SIZE_OUT => fc_udp_size,
580 FC_IDENT_OUT => fc_ident,
581 FC_FLAGS_OFFSET_OUT => fc_flags_offset,
582 FC_SOD_OUT => fc_sod,
583 FC_EOD_OUT => fc_eod,
584 FC_IP_PROTOCOL_OUT => fc_protocol,
585
586 DEST_MAC_ADDRESS_OUT => fc_dest_mac,
587 DEST_IP_ADDRESS_OUT => fc_dest_ip,
588 DEST_UDP_PORT_OUT => fc_dest_udp,
589 SRC_MAC_ADDRESS_OUT => fc_src_mac,
590 SRC_IP_ADDRESS_OUT => fc_src_ip,
591 SRC_UDP_PORT_OUT => fc_src_udp,
592
593
594 -- debug
595 DEBUG_OUT => open
596 );
597
598 -- Third stage: Frame Constructor
599 FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr
600 port map(
601 -- ports for user logic
602 RESET => RESET,
603 CLK => CLKSYS_IN,
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604 LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
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605 --
606 WR_EN_IN => fc_wr_en,
607 DATA_IN => fc_data,
608 START_OF_DATA_IN => fc_sod,
609 END_OF_DATA_IN => fc_eod,
610 IP_F_SIZE_IN => fc_ip_size,
611 UDP_P_SIZE_IN => fc_udp_size,
612 HEADERS_READY_OUT => fc_h_ready,
613 READY_OUT => fc_ready,
614 DEST_MAC_ADDRESS_IN => fc_dest_mac,
615 DEST_IP_ADDRESS_IN => fc_dest_ip,
616 DEST_UDP_PORT_IN => fc_dest_udp,
617 SRC_MAC_ADDRESS_IN => fc_src_mac,
618 SRC_IP_ADDRESS_IN => fc_src_ip,
619 SRC_UDP_PORT_IN => fc_src_udp,
620 FRAME_TYPE_IN => fc_type,
621 IHL_VERSION_IN => fc_ihl_version,
622 TOS_IN => fc_tos,
623 IDENTIFICATION_IN => fc_ident,
624 FLAGS_OFFSET_IN => fc_flags_offset,
625 TTL_IN => fc_ttl,
626 PROTOCOL_IN => fc_protocol,
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627 FRAME_DELAY_IN => (others => '0'), -- gk 09.12.10
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628 -- ports for packetTransmitter
629 RD_CLK => serdes_clk_125,
630 FT_DATA_OUT => ft_data,
631 FT_TX_EMPTY_OUT => ft_tx_empty,
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632 FT_TX_RD_EN_IN => mac_tx_read,
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633 FT_START_OF_PACKET_OUT => ft_start_of_packet,
634 FT_TX_DONE_IN => mac_tx_done,
635 FT_TX_DISCFRM_IN => mac_tx_discfrm,
636 -- debug ports
637 BSM_CONSTR_OUT => open,
638 BSM_TRANS_OUT => open,
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639 DEBUG_OUT => open
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640 );
641
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642 fc_ttl <= x"10";
643
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644 RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
645 port map(
646 CLK => CLKSYS_IN,
647 RESET => RESET,
648
649 -- signals to/from frame_receiver
650 RC_DATA_IN => fr_q,
651 FR_RD_EN_OUT => fr_rd_en,
652 FR_FRAME_VALID_IN => fr_frame_valid,
653 FR_GET_FRAME_OUT => fr_get_frame,
654 FR_FRAME_SIZE_IN => fr_frame_size,
655 FR_FRAME_PROTO_IN => fr_frame_proto,
656 FR_IP_PROTOCOL_IN => fr_ip_proto,
657
658 FR_SRC_MAC_ADDRESS_IN => fr_src_mac,
659 FR_DEST_MAC_ADDRESS_IN => fr_dest_mac,
660 FR_SRC_IP_ADDRESS_IN => fr_src_ip,
661 FR_DEST_IP_ADDRESS_IN => fr_dest_ip,
662 FR_SRC_UDP_PORT_IN => fr_src_udp,
663 FR_DEST_UDP_PORT_IN => fr_dest_udp,
664
665 -- signals to/from main controller
666 RC_RD_EN_IN => rc_rd_en,
667 RC_Q_OUT => rc_q,
668 RC_FRAME_WAITING_OUT => rc_frame_ready,
669 RC_LOADING_DONE_IN => rc_loading_done,
670 RC_FRAME_SIZE_OUT => rc_frame_size,
671 RC_FRAME_PROTO_OUT => rc_frame_proto,
672
673 RC_SRC_MAC_ADDRESS_OUT => rc_src_mac,
674 RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac,
675 RC_SRC_IP_ADDRESS_OUT => rc_src_ip,
676 RC_DEST_IP_ADDRESS_OUT => rc_dest_ip,
677 RC_SRC_UDP_PORT_OUT => rc_src_udp,
678 RC_DEST_UDP_PORT_OUT => rc_dest_udp,
679
680 -- statistics
681 FRAMES_RECEIVED_OUT => open,
682 BYTES_RECEIVED_OUT => open,
683
684
685 DEBUG_OUT => open
686 );
687
688
689 FRAME_TRANSMITTER: trb_net16_gbe_frame_trans
690 port map(
691 CLK => CLKSYS_IN,
692 RESET => RESET,
693 LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
694 TX_MAC_CLK => serdes_clk_125,
695 TX_EMPTY_IN => ft_tx_empty,
696 START_OF_PACKET_IN => ft_start_of_packet,
697 DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10
698
699 TX_FIFOAVAIL_OUT => mac_fifoavail,
700 TX_FIFOEOF_OUT => mac_fifoeof,
701 TX_FIFOEMPTY_OUT => mac_fifoempty,
702 TX_DONE_IN => mac_tx_done,
703 TX_STAT_EN_IN => mac_tx_staten,
704 TX_STATVEC_IN => mac_tx_statevec,
705 TX_DISCFRM_IN => mac_tx_discfrm,
706 -- Debug
707 BSM_INIT_OUT => open,
708 BSM_MAC_OUT => open,
709 BSM_TRANS_OUT => open,
710 DBG_RD_DONE_OUT => open,
711 DBG_INIT_DONE_OUT => open,
712 DBG_ENABLED_OUT => open,
713 DEBUG_OUT => open
714 );
715
716
717 FRAME_RECEIVER : trb_net16_gbe_frame_receiver
718 port map(
719 CLK => CLKSYS_IN,
720 RESET => RESET,
721 LINK_OK_IN => link_ok,
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722 ALLOW_RX_IN => '1', --allow_rx,
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723 RX_MAC_CLK => serdes_rx_clk,
724
725 -- input signals from TS_MAC
726 MAC_RX_EOF_IN => mac_rx_eof,
727 MAC_RX_ER_IN => mac_rx_er,
728 MAC_RXD_IN => mac_rxd,
729 MAC_RX_EN_IN => mac_rx_en,
730 MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err,
731 MAC_RX_FIFO_FULL_OUT => mac_rx_fifo_full,
732 MAC_RX_STAT_EN_IN => mac_rx_stat_en,
733 MAC_RX_STAT_VEC_IN => mac_rx_stat_vec,
734 -- output signal to control logic
735 FR_Q_OUT => fr_q,
736 FR_RD_EN_IN => fr_rd_en,
737 FR_FRAME_VALID_OUT => fr_frame_valid,
738 FR_GET_FRAME_IN => fr_get_frame,
739 FR_FRAME_SIZE_OUT => fr_frame_size,
740 FR_FRAME_PROTO_OUT => fr_frame_proto,
741 FR_IP_PROTOCOL_OUT => fr_ip_proto,
742 FR_ALLOWED_TYPES_IN => fr_allowed_types,
743 FR_ALLOWED_IP_IN => fr_allowed_ip,
744 FR_ALLOWED_UDP_IN => fr_allowed_udp,
745 FR_VLAN_ID_IN => vlan_id,
746
747 FR_SRC_MAC_ADDRESS_OUT => fr_src_mac,
748 FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac,
749 FR_SRC_IP_ADDRESS_OUT => fr_src_ip,
750 FR_DEST_IP_ADDRESS_OUT => fr_dest_ip,
751 FR_SRC_UDP_PORT_OUT => fr_src_udp,
752 FR_DEST_UDP_PORT_OUT => fr_dest_udp,
753
754 DEBUG_OUT => open
755 );
756
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grzegorzkorcyl authored Mar 30, 2012
757 serdes_rx_clk <= CLKGBE_IN when g_SIMULATE = 1 else serdes_rx_clk_a;
758 serdes_clk_125 <= CLKGBE_IN when g_SIMULATE = 1 else serdes_clk_125_a;
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759
760 MAC: tsmac34
761 port map(
762 ----------------- clock and reset port declarations ------------------
763 hclk => CLKSYS_IN,
764 txmac_clk => serdes_clk_125,
765 rxmac_clk => serdes_rx_clk, --serdes_clk_125,
766 reset_n => GSR_N,
767 txmac_clk_en => mac_tx_clk_en,
768 rxmac_clk_en => mac_rx_clk_en,
769 ------------------- Input signals to the GMII ---------------- NOT USED
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770 rxd => pcs_rxd_qq,
771 rx_dv => pcs_rx_en_qq,
772 rx_er => pcs_rx_er_qq,
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773 col => mac_col,
774 crs => mac_crs,
775 -------------------- Input signals to the CPU I/F -------------------
776 haddr => mac_haddr,
777 hdatain => mac_hdataout,
778 hcs_n => mac_hcs,
779 hwrite_n => mac_hwrite,
780 hread_n => mac_hread,
781 ---------------- Input signals to the Tx MAC FIFO I/F ---------------
782 tx_fifodata => ft_data(7 downto 0),
783 tx_fifoavail => mac_fifoavail,
784 tx_fifoeof => mac_fifoeof,
785 tx_fifoempty => mac_fifoempty,
786 tx_sndpaustim => x"0000",
787 tx_sndpausreq => '0',
788 tx_fifoctrl => '0', -- always data frame
789 ---------------- Input signals to the Rx MAC FIFO I/F ---------------
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790 rx_fifo_full => mac_rx_fifo_full,
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791 ignore_pkt => '0',
792 ---------------- Output signals from the GMII -----------------------
793 txd => pcs_txd,
794 tx_en => pcs_tx_en,
795 tx_er => pcs_tx_er,
796 ----------------- Output signals from the CPU I/F -------------------
797 hdataout => open,
798 hdataout_en_n => mac_hdata_en,
799 hready_n => mac_hready,
800 cpu_if_gbit_en => tsmac_gbit_en,
801 ------------- Output signals from the Tx MAC FIFO I/F ---------------
802 tx_macread => mac_tx_read,
803 tx_discfrm => mac_tx_discfrm,
804 tx_staten => mac_tx_staten, -- gk 08.06.10
805 tx_statvec => mac_tx_statevec, -- gk 08.06.10
806 tx_done => mac_tx_done,
807 ------------- Output signals from the Rx MAC FIFO I/F ---------------
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grzegorzkorcyl authored Mar 28, 2012
808 rx_fifo_error => mac_rx_fifo_err,
809 rx_stat_vector => mac_rx_stat_vec,
810 rx_dbout => mac_rxd,
811 rx_write => mac_rx_en,
812 rx_stat_en => mac_rx_stat_en,
813 rx_eof => mac_rx_eof,
814 rx_error => mac_rx_er
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815 );
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816
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817
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818 SYNC_GMII_RX_PROC : process(serdes_rx_clk)
819 begin
820 if rising_edge(serdes_rx_clk) then
821 pcs_rxd_q <= pcs_rxd;
822 pcs_rx_en_q <= pcs_rx_en;
823 pcs_rx_er_q <= pcs_rx_er;
824
825 pcs_rxd_qq <= pcs_rxd_q;
826 pcs_rx_en_qq <= pcs_rx_en_q;
827 pcs_rx_er_qq <= pcs_rx_er_q;
828 end if;
829 end process SYNC_GMII_RX_PROC;
830
831 SYNC_GMII_TX_PROC : process(serdes_clk_125)
832 begin
833 if rising_edge(serdes_clk_125) then
834 pcs_txd_q <= pcs_txd;
835 pcs_tx_en_q <= pcs_tx_en;
836 pcs_tx_er_q <= pcs_tx_er;
837
838 pcs_txd_qq <= pcs_txd_q;
839 pcs_tx_en_qq <= pcs_tx_en_q;
840 pcs_tx_er_qq <= pcs_tx_er_q;
841 end if;
842 end process SYNC_GMII_TX_PROC;
843
844 PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b
845 generic map(
846 USE_125MHZ_EXTCLK => 0
847 )
848 port map(
849 RESET => RESET,
850 GSR_N => GSR_N,
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851 CLK_125_OUT => serdes_clk_125_a,
852 CLK_125_RX_OUT => serdes_rx_clk_a,
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853 CLK_125_IN => CLKGBE_IN,
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854 FT_TX_CLK_EN_OUT => mac_tx_clk_en,
855 FT_RX_CLK_EN_OUT => mac_rx_clk_en,
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856 --connection to frame transmitter (tsmac)
857 FT_COL_OUT => mac_col,
858 FT_CRS_OUT => mac_crs,
859 FT_TXD_IN => pcs_txd_qq,
860 FT_TX_EN_IN => pcs_tx_en_qq,
861 FT_TX_ER_IN => pcs_tx_er_qq,
862 FT_RXD_OUT => pcs_rxd,
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863 FT_RX_EN_OUT => pcs_rx_en,
864 FT_RX_ER_OUT => pcs_rx_er,
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865
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866 -- Autonegotiation stuff
867 MR_ADV_ABILITY_IN => x"0020", -- full duplex only
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868 MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability,
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869 MR_AN_PAGE_RX_OUT => pcs_an_page_rx,
870 MR_AN_COMPLETE_OUT => pcs_an_complete,
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871 MR_RESET_IN => RESET,
872 MR_MODE_IN => '0', --MR_MODE_IN,
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873 MR_AN_ENABLE_IN => '1', -- do autonegotiation
874 MR_RESTART_AN_IN => '0', --MR_RESTART_IN,
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grzegorzkorcyl authored Mar 5, 2012
875
876 SD_RX_CLK_IN => SD_RX_CLK_IN,
877 SD_TX_DATA_OUT => SD_TX_DATA_OUT,
878 SD_TX_KCNTL_OUT => SD_TX_KCNTL_OUT,
879 SD_TX_CORRECT_DISP_OUT => SD_TX_CORRECT_DISP_OUT,
880 SD_RX_DATA_IN => SD_RX_DATA_IN,
881 SD_RX_KCNTL_IN => SD_RX_KCNTL_IN,
882 SD_RX_DISP_ERROR_IN => SD_RX_DISP_ERROR_IN,
883 SD_RX_CV_ERROR_IN => SD_RX_CV_ERROR_IN,
884 SD_RX_SERDES_RST_OUT => SD_RX_SERDES_RST_OUT,
885 SD_RX_PCS_RST_OUT => SD_RX_PCS_RST_OUT,
886 SD_TX_PCS_RST_OUT => SD_TX_PCS_RST_OUT,
887 SD_RX_LOS_IN => SD_RX_LOS_IN,
888 SD_SIGNAL_DETECTED_IN => SD_SIGNAL_DETECTED_IN,
889 SD_RX_CDR_IN => SD_RX_CDR_IN,
890 SD_TX_PLL_LOL_IN => SD_TX_PLL_LOL_IN,
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891 SD_QUAD_RST_OUT => SD_QUAD_RST_OUT,
892 SD_XMIT_OUT => SD_XMIT_OUT
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893 );
894
895
896 -- FrameConstructor fixed magic values
897 --fc_type <= x"0008";
898 fc_ihl_version <= x"45";
899 fc_tos <= x"10";
900
901 -- FrameConstructor fixed magic values
902 --fc_type <= x"0008";
903 fc_ihl_version <= x"45";
904 fc_tos <= x"10";
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grzegorzkorcyl authored Mar 6, 2012
905
906 LINK_OK_OUT <= link_ok;
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grzegorzkorcyl authored Mar 27, 2012
907
908
909 -- for debug only
910 --TEST_PORT_OUT(7 downto 0) <= ft_data;
911 --TEST_PORT_OUT(8) <= mac_fifoeof;
912 --TEST_PORT_OUT(9) <= mac_fifoavail;
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913
914 end architecture CNTester_module;
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