Navigation Menu

Skip to content

Commit

Permalink
update
Browse files Browse the repository at this point in the history
  • Loading branch information
grzegorzkorcyl authored and grzegorzkorcyl committed Mar 5, 2012
1 parent 042c4a1 commit e88e265
Show file tree
Hide file tree
Showing 10 changed files with 584 additions and 583 deletions.
98 changes: 91 additions & 7 deletions CNTester_Main.vhd
View file
Expand Up @@ -14,21 +14,105 @@ use work.trb_net_gbe_protocols.all;

entity CNTester_Main is
port (
CLKSYS_IN : in std_logic;
RESET : in std_logic;
CLKSYS_IN : in std_logic;
RESET : in std_logic;

GENERATE_OUT : out std_logic_vector(2 downto 0);
TIMESTAMP_OUT : out std_logic_vector(31 downto 0);
DEST_ADDR_OUT : out std_logic_vector(15 downto 0)
GENERATE_OUT : out std_logic_vector(2 downto 0);
TIMESTAMP_OUT : out std_logic_vector(31 downto 0);
DEST_ADDR_OUT : out std_logic_vector(15 downto 0);
SIZE_OUT : out std_logic_vector(15 downto 0);

SENDERS_FREE_IN : in std_logic_vector(2 downto 0)
);
end entity CNTester_Main;

architecture CNTester_Main of CNTester_Main is

type generate_states is (IDLE, GENERATE_SENDER, GENERATE_SIZE, ACTIVATE);
signal generate_current_state, generate_next_state : generate_states;

signal generate_en : std_logic;
signal values : std_logic_vector(31 downto 0);

signal timer : std_logic_vector(31 downto 0);

begin

GENERATE_OUT <= (others => '0');
TIMESTAMP_OUT <= (others => '0');
RAND : CNTester_random
port map(
CLK_IN => CLKSYS_IN,
RESET => RESET,
GENERATE_IN => generate_en,
RANDOM_OUT => values
);


GENERATE_MACHINE_PROC : process(CLKSYS_IN)
begin
if rising_edge(CLKSYS_IN) then
if (RESET = '1') then
generate_current_state <= IDLE;
else
generate_current_state <= generate_next_state;
end if;
end if;
end process GENERATE_MACHINE_PROC;

GENERATE_MACHINE : process(generate_current_state, SENDERS_FREE_IN)
begin

case (generate_current_state) is

when IDLE =>
if (SENDERS_FREE_IN = "000") then
generate_next_state <= GENERATE_SENDER;
else
generate_next_state <= IDLE;
end if;

when GENERATE_SENDER =>
generate_next_state <= GENERATE_SIZE;

when GENERATE_SIZE =>
generate_next_state <= ACTIVATE;

when ACTIVATE =>
generate_next_state <= IDLE;

end case;

end process GENERATE_MACHINE;

generate_en <= '1' when generate_current_state = GENERATE_SENDER or generate_current_state = GENERATE_SIZE else '0';

GENERATE_OUT(0) <= '1' when values(20) = '1' and generate_current_state = GENERATE_SIZE else '0';
GENERATE_OUT(1) <= '1' when values(6) = '1' and generate_current_state = GENERATE_SIZE else '0';
GENERATE_OUT(2) <= '1' when values(7) = '1' and generate_current_state = GENERATE_SIZE else '0';

SIZE_PROC : process(CLKSYS_IN)
begin
if rising_edge(CLKSYS_IN) then
if (RESET = '1') then
SIZE_OUT <= (others => '0');
elsif (generate_current_state = GENERATE_SIZE) then
SIZE_OUT <= "0000" & values(7 downto 0) & "1111";
end if;
end if;
end process SIZE_PROC;

TIMER_PROC : process(CLKSYS_IN)
begin
if rising_edge(CLKSYS_IN) then
if (RESET = '1') then
timer <= (others => '0');
else
timer <= timer + x"1";
end if;
end if;
end process TIMER_PROC;

TIMESTAMP_OUT <= timer;

DEST_ADDR_OUT <= (others => '0');

end architecture CNTester_Main;
97 changes: 44 additions & 53 deletions CNTester_module.vhd
View file
Expand Up @@ -19,23 +19,29 @@ entity CNTester_module is
RESET : in std_logic;
GSR_N : in std_logic;

SFP_RXD_P_IN : in std_logic;
SFP_RXD_N_IN : in std_logic;
SFP_TXD_P_OUT : out std_logic;
SFP_TXD_N_OUT : out std_logic;
SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
SFP_TXDIS_OUT : out std_logic; -- SFP disable

TIMESTAMP_IN : in std_logic_vector(31 downto 0);
DEST_ADDR_IN : in std_logic_vector(15 downto 0);
GENERATE_PACKET_IN : in std_logic;
SIZE_IN : in std_logic_vector(15 downto 0);
BUSY_OUT : out std_logic;

LED_GREEN : out std_logic;
LED_ORANGE : out std_logic;
LED_RED : out std_logic;
LED_YELLOW : out std_logic

-- serdes io
SD_RX_CLK_IN : in std_logic;
SD_TX_DATA_OUT : out std_logic_vector(7 downto 0);
SD_TX_KCNTL_OUT : out std_logic;
SD_TX_CORRECT_DISP_OUT : out std_logic;
SD_RX_DATA_IN : in std_logic_vector(7 downto 0);
SD_RX_KCNTL_IN : in std_logic;
SD_RX_DISP_ERROR_IN : in std_logic;
SD_RX_CV_ERROR_IN : in std_logic;
SD_RX_SERDES_RST_OUT : out std_logic;
SD_RX_PCS_RST_OUT : out std_logic;
SD_TX_PCS_RST_OUT : out std_logic;
SD_RX_LOS_IN : in std_logic;
SD_SIGNAL_DETECTED_IN : in std_logic;
SD_RX_CDR_IN : in std_logic;
SD_TX_PLL_LOL_IN : in std_logic;
SD_QUAD_RST_OUT : out std_logic
);
end entity CNTester_module;

Expand Down Expand Up @@ -385,7 +391,6 @@ signal pcs_tx_en_q, pcs_tx_er_q, pcs_rx_en_q, pcs_rx_er_q, mac_col_q, mac_crs_q
signal pcs_txd_qq, pcs_rxd_qq : std_logic_vector(7 downto 0);
signal pcs_tx_en_qq, pcs_tx_er_qq, pcs_rx_en_qq, pcs_rx_er_qq, mac_col_qq, mac_crs_qq : std_logic;

signal cnt1, cnt2 : std_logic_vector(31 downto 0);

begin

Expand Down Expand Up @@ -442,6 +447,13 @@ MAIN_CONTROL : trb_net16_gbe_main_control

-- signals to/from hub
MC_UNIQUE_ID_IN => (others => '0'),

CNT_GENERATE_PACKET_IN => GENERATE_PACKET_IN,
CNT_TIMESTAMP_IN => TIMESTAMP_IN,
CNT_DEST_ADDR_IN => DEST_ADDR_IN,
CNT_SIZE_IN => SIZE_IN,
CNT_BUSY_OUT => BUSY_OUT,

GSC_CLK_IN => '0',
GSC_INIT_DATAREADY_OUT => open,
GSC_INIT_DATA_OUT => open,
Expand Down Expand Up @@ -808,16 +820,7 @@ MAC: tsmac34
FT_RXD_OUT => pcs_rxd,
FT_RX_EN_OUT => pcs_rx_en,
FT_RX_ER_OUT => pcs_rx_er,
--SFP Connection
SD_RXD_P_IN => SFP_RXD_P_IN,
SD_RXD_N_IN => SFP_RXD_N_IN,
SD_TXD_P_OUT => SFP_TXD_P_OUT,
SD_TXD_N_OUT => SFP_TXD_N_OUT,
SD_REFCLK_P_IN => '0',
SD_REFCLK_N_IN => '1',
SD_PRSNT_N_IN => SFP_PRSNT_N_IN,
SD_LOS_IN => SFP_LOS_IN,
SD_TXDIS_OUT => SFP_TXDIS_OUT,

-- Autonegotiation stuff
MR_ADV_ABILITY_IN => x"0020", -- full duplex only
MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability,
Expand All @@ -827,37 +830,25 @@ MAC: tsmac34
MR_MODE_IN => '0', --MR_MODE_IN,
MR_AN_ENABLE_IN => '1', -- do autonegotiation
MR_RESTART_AN_IN => '0', --MR_RESTART_IN,
-- Status and control port
STAT_OP => open,
CTRL_OP => x"0000",
STAT_DEBUG => pcs_stat_debug, --open,
CTRL_DEBUG => x"0000_0000_0000_0000"

SD_RX_CLK_IN => SD_RX_CLK_IN,
SD_TX_DATA_OUT => SD_TX_DATA_OUT,
SD_TX_KCNTL_OUT => SD_TX_KCNTL_OUT,
SD_TX_CORRECT_DISP_OUT => SD_TX_CORRECT_DISP_OUT,
SD_RX_DATA_IN => SD_RX_DATA_IN,
SD_RX_KCNTL_IN => SD_RX_KCNTL_IN,
SD_RX_DISP_ERROR_IN => SD_RX_DISP_ERROR_IN,
SD_RX_CV_ERROR_IN => SD_RX_CV_ERROR_IN,
SD_RX_SERDES_RST_OUT => SD_RX_SERDES_RST_OUT,
SD_RX_PCS_RST_OUT => SD_RX_PCS_RST_OUT,
SD_TX_PCS_RST_OUT => SD_TX_PCS_RST_OUT,
SD_RX_LOS_IN => SD_RX_LOS_IN,
SD_SIGNAL_DETECTED_IN => SD_SIGNAL_DETECTED_IN,
SD_RX_CDR_IN => SD_RX_CDR_IN,
SD_TX_PLL_LOL_IN => SD_TX_PLL_LOL_IN,
SD_QUAD_RST_OUT => SD_QUAD_RST_OUT
);

CNT1_PROC : process (serdes_clk_125) is
begin
if rising_edge(serdes_clk_125) then
if (RESET = '1') then
cnt1 <= (others => '0');
else
cnt1 <= cnt1 + x"1";
end if;
end if;
end process CNT1_PROC ;

CNT2_PROC : process (serdes_rx_clk) is
begin
if rising_edge(serdes_rx_clk) then
if (RESET = '1') then
cnt2 <= (others => '0');
else
cnt2 <= cnt2 + x"1";
end if;
end if;
end process CNT2_PROC ;

LED_GREEN <= cnt1(24);
LED_ORANGE <= cnt2(24);

-- FrameConstructor fixed magic values
--fc_type <= x"0008";
Expand Down
49 changes: 29 additions & 20 deletions CNTester_random.vhd
View file
Expand Up @@ -2,32 +2,41 @@ library ieee;
use ieee.std_logic_1164.all;

entity CNTester_random is
generic ( width : integer := 32 );
port (
CLK_IN : in std_logic;
RESET : in std_logic;
GENERATE_IN : in std_logic;
RANDOM_OUT : out std_logic_vector (width-1 downto 0) --output vector
RANDOM_OUT : out std_logic_vector (31 downto 0)
);
end entity CNTester_random;

architecture CNTester_random of CNTester_random is

begin

RAND_PROC : process(CLK_IN)
variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');
variable temp : std_logic := '0';

begin
if(rising_edge(CLK_IN)) then
if (GENERATE_IN = '1') then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
end if;
end if;

RANDOM_OUT <= rand_temp;
end process;

signal lfsr: std_logic_vector (31 downto 0);
signal d0 : std_logic;

begin

d0 <= lfsr(17) xnor lfsr(15);

-- process(lfsr) begin
-- if(lfsr = x"359") then
-- lfsr_equal <= '1';
-- else
-- lfsr_equal <= '0';
-- end if;
-- end process;

process (CLK_IN,RESET) begin
if (RESET = '1') then
lfsr <= (others => '0');
elsif (CLK_IN'EVENT and CLK_IN = '1') then
if (GENERATE_IN = '1') then
lfsr <= lfsr(30 downto 0) & d0;
end if;
end if;
end process;

RANDOM_OUT <= lfsr;

end architecture CNTester_random;

0 comments on commit e88e265

Please sign in to comment.