From e88e265012b279205ad1e692c00c7862490bff08 Mon Sep 17 00:00:00 2001 From: grzegorzkorcyl Date: Mon, 5 Mar 2012 14:07:29 +0100 Subject: [PATCH] update --- CNTester_Main.vhd | 98 +++- CNTester_module.vhd | 97 ++-- CNTester_random.vhd | 49 +- trb3_central.vhd | 193 ++++++- trb_net16_gbe_main_control.vhd | 12 + trb_net16_gbe_protocol_selector.vhd | 12 +- ...t16_gbe_response_constructor_CNTeseter.vhd | 26 +- trb_net16_med_ecp_sfp_gbe_8b.vhd | 471 ++---------------- trb_net_gbe_components.vhd | 207 ++++++-- trb_net_gbe_protocols.vhd | 2 +- 10 files changed, 584 insertions(+), 583 deletions(-) diff --git a/CNTester_Main.vhd b/CNTester_Main.vhd index afb6b66..31ad2df 100644 --- a/CNTester_Main.vhd +++ b/CNTester_Main.vhd @@ -14,21 +14,105 @@ use work.trb_net_gbe_protocols.all; entity CNTester_Main is port ( - CLKSYS_IN : in std_logic; - RESET : in std_logic; + CLKSYS_IN : in std_logic; + RESET : in std_logic; - GENERATE_OUT : out std_logic_vector(2 downto 0); - TIMESTAMP_OUT : out std_logic_vector(31 downto 0); - DEST_ADDR_OUT : out std_logic_vector(15 downto 0) + GENERATE_OUT : out std_logic_vector(2 downto 0); + TIMESTAMP_OUT : out std_logic_vector(31 downto 0); + DEST_ADDR_OUT : out std_logic_vector(15 downto 0); + SIZE_OUT : out std_logic_vector(15 downto 0); + + SENDERS_FREE_IN : in std_logic_vector(2 downto 0) ); end entity CNTester_Main; architecture CNTester_Main of CNTester_Main is + +type generate_states is (IDLE, GENERATE_SENDER, GENERATE_SIZE, ACTIVATE); +signal generate_current_state, generate_next_state : generate_states; + +signal generate_en : std_logic; +signal values : std_logic_vector(31 downto 0); + +signal timer : std_logic_vector(31 downto 0); begin - GENERATE_OUT <= (others => '0'); - TIMESTAMP_OUT <= (others => '0'); + RAND : CNTester_random + port map( + CLK_IN => CLKSYS_IN, + RESET => RESET, + GENERATE_IN => generate_en, + RANDOM_OUT => values + ); + + + GENERATE_MACHINE_PROC : process(CLKSYS_IN) + begin + if rising_edge(CLKSYS_IN) then + if (RESET = '1') then + generate_current_state <= IDLE; + else + generate_current_state <= generate_next_state; + end if; + end if; + end process GENERATE_MACHINE_PROC; + + GENERATE_MACHINE : process(generate_current_state, SENDERS_FREE_IN) + begin + + case (generate_current_state) is + + when IDLE => + if (SENDERS_FREE_IN = "000") then + generate_next_state <= GENERATE_SENDER; + else + generate_next_state <= IDLE; + end if; + + when GENERATE_SENDER => + generate_next_state <= GENERATE_SIZE; + + when GENERATE_SIZE => + generate_next_state <= ACTIVATE; + + when ACTIVATE => + generate_next_state <= IDLE; + + end case; + + end process GENERATE_MACHINE; + + generate_en <= '1' when generate_current_state = GENERATE_SENDER or generate_current_state = GENERATE_SIZE else '0'; + + GENERATE_OUT(0) <= '1' when values(20) = '1' and generate_current_state = GENERATE_SIZE else '0'; + GENERATE_OUT(1) <= '1' when values(6) = '1' and generate_current_state = GENERATE_SIZE else '0'; + GENERATE_OUT(2) <= '1' when values(7) = '1' and generate_current_state = GENERATE_SIZE else '0'; + + SIZE_PROC : process(CLKSYS_IN) + begin + if rising_edge(CLKSYS_IN) then + if (RESET = '1') then + SIZE_OUT <= (others => '0'); + elsif (generate_current_state = GENERATE_SIZE) then + SIZE_OUT <= "0000" & values(7 downto 0) & "1111"; + end if; + end if; + end process SIZE_PROC; + + TIMER_PROC : process(CLKSYS_IN) + begin + if rising_edge(CLKSYS_IN) then + if (RESET = '1') then + timer <= (others => '0'); + else + timer <= timer + x"1"; + end if; + end if; + end process TIMER_PROC; + + TIMESTAMP_OUT <= timer; + DEST_ADDR_OUT <= (others => '0'); end architecture CNTester_Main; diff --git a/CNTester_module.vhd b/CNTester_module.vhd index a5e44df..e31798e 100644 --- a/CNTester_module.vhd +++ b/CNTester_module.vhd @@ -19,23 +19,29 @@ entity CNTester_module is RESET : in std_logic; GSR_N : in std_logic; - SFP_RXD_P_IN : in std_logic; - SFP_RXD_N_IN : in std_logic; - SFP_TXD_P_OUT : out std_logic; - SFP_TXD_N_OUT : out std_logic; - SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SFP_TXDIS_OUT : out std_logic; -- SFP disable - TIMESTAMP_IN : in std_logic_vector(31 downto 0); DEST_ADDR_IN : in std_logic_vector(15 downto 0); GENERATE_PACKET_IN : in std_logic; + SIZE_IN : in std_logic_vector(15 downto 0); + BUSY_OUT : out std_logic; - LED_GREEN : out std_logic; - LED_ORANGE : out std_logic; - LED_RED : out std_logic; - LED_YELLOW : out std_logic - + -- serdes io + SD_RX_CLK_IN : in std_logic; + SD_TX_DATA_OUT : out std_logic_vector(7 downto 0); + SD_TX_KCNTL_OUT : out std_logic; + SD_TX_CORRECT_DISP_OUT : out std_logic; + SD_RX_DATA_IN : in std_logic_vector(7 downto 0); + SD_RX_KCNTL_IN : in std_logic; + SD_RX_DISP_ERROR_IN : in std_logic; + SD_RX_CV_ERROR_IN : in std_logic; + SD_RX_SERDES_RST_OUT : out std_logic; + SD_RX_PCS_RST_OUT : out std_logic; + SD_TX_PCS_RST_OUT : out std_logic; + SD_RX_LOS_IN : in std_logic; + SD_SIGNAL_DETECTED_IN : in std_logic; + SD_RX_CDR_IN : in std_logic; + SD_TX_PLL_LOL_IN : in std_logic; + SD_QUAD_RST_OUT : out std_logic ); end entity CNTester_module; @@ -385,7 +391,6 @@ signal pcs_tx_en_q, pcs_tx_er_q, pcs_rx_en_q, pcs_rx_er_q, mac_col_q, mac_crs_q signal pcs_txd_qq, pcs_rxd_qq : std_logic_vector(7 downto 0); signal pcs_tx_en_qq, pcs_tx_er_qq, pcs_rx_en_qq, pcs_rx_er_qq, mac_col_qq, mac_crs_qq : std_logic; -signal cnt1, cnt2 : std_logic_vector(31 downto 0); begin @@ -442,6 +447,13 @@ MAIN_CONTROL : trb_net16_gbe_main_control -- signals to/from hub MC_UNIQUE_ID_IN => (others => '0'), + + CNT_GENERATE_PACKET_IN => GENERATE_PACKET_IN, + CNT_TIMESTAMP_IN => TIMESTAMP_IN, + CNT_DEST_ADDR_IN => DEST_ADDR_IN, + CNT_SIZE_IN => SIZE_IN, + CNT_BUSY_OUT => BUSY_OUT, + GSC_CLK_IN => '0', GSC_INIT_DATAREADY_OUT => open, GSC_INIT_DATA_OUT => open, @@ -808,16 +820,7 @@ MAC: tsmac34 FT_RXD_OUT => pcs_rxd, FT_RX_EN_OUT => pcs_rx_en, FT_RX_ER_OUT => pcs_rx_er, - --SFP Connection - SD_RXD_P_IN => SFP_RXD_P_IN, - SD_RXD_N_IN => SFP_RXD_N_IN, - SD_TXD_P_OUT => SFP_TXD_P_OUT, - SD_TXD_N_OUT => SFP_TXD_N_OUT, - SD_REFCLK_P_IN => '0', - SD_REFCLK_N_IN => '1', - SD_PRSNT_N_IN => SFP_PRSNT_N_IN, - SD_LOS_IN => SFP_LOS_IN, - SD_TXDIS_OUT => SFP_TXDIS_OUT, + -- Autonegotiation stuff MR_ADV_ABILITY_IN => x"0020", -- full duplex only MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, @@ -827,37 +830,25 @@ MAC: tsmac34 MR_MODE_IN => '0', --MR_MODE_IN, MR_AN_ENABLE_IN => '1', -- do autonegotiation MR_RESTART_AN_IN => '0', --MR_RESTART_IN, - -- Status and control port - STAT_OP => open, - CTRL_OP => x"0000", - STAT_DEBUG => pcs_stat_debug, --open, - CTRL_DEBUG => x"0000_0000_0000_0000" + + SD_RX_CLK_IN => SD_RX_CLK_IN, + SD_TX_DATA_OUT => SD_TX_DATA_OUT, + SD_TX_KCNTL_OUT => SD_TX_KCNTL_OUT, + SD_TX_CORRECT_DISP_OUT => SD_TX_CORRECT_DISP_OUT, + SD_RX_DATA_IN => SD_RX_DATA_IN, + SD_RX_KCNTL_IN => SD_RX_KCNTL_IN, + SD_RX_DISP_ERROR_IN => SD_RX_DISP_ERROR_IN, + SD_RX_CV_ERROR_IN => SD_RX_CV_ERROR_IN, + SD_RX_SERDES_RST_OUT => SD_RX_SERDES_RST_OUT, + SD_RX_PCS_RST_OUT => SD_RX_PCS_RST_OUT, + SD_TX_PCS_RST_OUT => SD_TX_PCS_RST_OUT, + SD_RX_LOS_IN => SD_RX_LOS_IN, + SD_SIGNAL_DETECTED_IN => SD_SIGNAL_DETECTED_IN, + SD_RX_CDR_IN => SD_RX_CDR_IN, + SD_TX_PLL_LOL_IN => SD_TX_PLL_LOL_IN, + SD_QUAD_RST_OUT => SD_QUAD_RST_OUT ); - -CNT1_PROC : process (serdes_clk_125) is -begin - if rising_edge(serdes_clk_125) then - if (RESET = '1') then - cnt1 <= (others => '0'); - else - cnt1 <= cnt1 + x"1"; - end if; - end if; -end process CNT1_PROC ; - -CNT2_PROC : process (serdes_rx_clk) is -begin - if rising_edge(serdes_rx_clk) then - if (RESET = '1') then - cnt2 <= (others => '0'); - else - cnt2 <= cnt2 + x"1"; - end if; - end if; -end process CNT2_PROC ; -LED_GREEN <= cnt1(24); -LED_ORANGE <= cnt2(24); -- FrameConstructor fixed magic values --fc_type <= x"0008"; diff --git a/CNTester_random.vhd b/CNTester_random.vhd index a870aa5..e54c1cf 100644 --- a/CNTester_random.vhd +++ b/CNTester_random.vhd @@ -2,32 +2,41 @@ library ieee; use ieee.std_logic_1164.all; entity CNTester_random is - generic ( width : integer := 32 ); port ( CLK_IN : in std_logic; + RESET : in std_logic; GENERATE_IN : in std_logic; - RANDOM_OUT : out std_logic_vector (width-1 downto 0) --output vector + RANDOM_OUT : out std_logic_vector (31 downto 0) ); end entity CNTester_random; architecture CNTester_random of CNTester_random is - -begin - -RAND_PROC : process(CLK_IN) - variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0'); - variable temp : std_logic := '0'; - -begin - if(rising_edge(CLK_IN)) then - if (GENERATE_IN = '1') then - temp := rand_temp(width-1) xor rand_temp(width-2); - rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0); - rand_temp(0) := temp; - end if; - end if; - - RANDOM_OUT <= rand_temp; -end process; + +signal lfsr: std_logic_vector (31 downto 0); +signal d0 : std_logic; + +begin + + d0 <= lfsr(17) xnor lfsr(15); + +-- process(lfsr) begin +-- if(lfsr = x"359") then +-- lfsr_equal <= '1'; +-- else +-- lfsr_equal <= '0'; +-- end if; +-- end process; + + process (CLK_IN,RESET) begin + if (RESET = '1') then + lfsr <= (others => '0'); + elsif (CLK_IN'EVENT and CLK_IN = '1') then + if (GENERATE_IN = '1') then + lfsr <= lfsr(30 downto 0) & d0; + end if; + end if; + end process; + + RANDOM_OUT <= lfsr; end architecture CNTester_random; \ No newline at end of file diff --git a/trb3_central.vhd b/trb3_central.vhd index bc988ae..c5183f3 100644 --- a/trb3_central.vhd +++ b/trb3_central.vhd @@ -254,6 +254,18 @@ signal gsc_busy : std_logic; signal mc_unique_id : std_logic_vector(63 downto 0); +signal senders_free, activate_sender : std_logic_vector(2 downto 0); +signal timestamp : std_logic_vector(31 downto 0); +signal dest_addr, size : std_logic_vector(15 downto 0); + +signal sd_rx_clk, sd_quad_rst : std_logic_vector(3 downto 0); +signal sd_tx_k, sd_xmit, sd_tx_disp, sd_rx_k, sd_rx_disp, sd_cv_err, sd_rx_serdes_rst, sd_tx_pcs_rst, sd_rx_pcs_rst, sd_rx_los, sd_rx_cdr, sd_signal_detected : std_logic_vector(3 downto 0); + +type arr is array(3 downto 0) of std_logic_vector(7 downto 0); +signal sd_tx_data, sd_rx_data : arr; + +signal sd_tx_pll_lol, sd1_quad_rst : std_logic; + begin @@ -262,9 +274,12 @@ MAIN : CNTester_Main CLKSYS_IN => clk_100_i, RESET => reset_i, - GENERATE_OUT => open, - TIMESTAMP_OUT => open, - DEST_ADDR_OUT => open + GENERATE_OUT => activate_sender, + TIMESTAMP_OUT => timestamp, + DEST_ADDR_OUT => dest_addr, + SIZE_OUT => size, + + SENDERS_FREE_IN => senders_free ); @@ -275,19 +290,171 @@ LINK_1 : CNTester_module RESET => reset_i, GSR_N => GSR_N, - SFP_RXD_P_IN => SFP_RX_P(5), - SFP_RXD_N_IN => SFP_RX_N(5), - SFP_TXD_P_OUT => SFP_TX_P(5), - SFP_TXD_N_OUT => SFP_TX_N(5), - SFP_PRSNT_N_IN => SFP_MOD0(5), - SFP_LOS_IN => SFP_LOS(5), - SFP_TXDIS_OUT => SFP_TXDIS(5), + -- serdes io + SD_RX_CLK_IN => sd_rx_clk(0), + SD_TX_DATA_OUT => sd_tx_data(0), + SD_TX_KCNTL_OUT => sd_tx_k(0), + SD_TX_CORRECT_DISP_OUT => sd_tx_disp(0), + SD_RX_DATA_IN => sd_rx_data(0), + SD_RX_KCNTL_IN => sd_rx_k(0), + SD_RX_DISP_ERROR_IN => sd_rx_disp(0), + SD_RX_CV_ERROR_IN => sd_cv_err(0), + SD_RX_SERDES_RST_OUT => sd_rx_serdes_rst(0), + SD_RX_PCS_RST_OUT => sd_rx_pcs_rst(0), + SD_TX_PCS_RST_OUT => sd_tx_pcs_rst(0), + SD_RX_LOS_IN => sd_rx_los(0), + SD_SIGNAL_DETECTED_IN => sd_signal_detected(0), + SD_RX_CDR_IN => sd_rx_cdr(0), + SD_TX_PLL_LOL_IN => sd_tx_pll_lol, + SD_QUAD_RST_OUT => sd_quad_rst(0), - TIMESTAMP_IN => (others => '0'), - DEST_ADDR_IN => (others => '0'), - GENERATE_PACKET_IN => '0' + TIMESTAMP_IN => timestamp, + DEST_ADDR_IN => dest_addr, + GENERATE_PACKET_IN => activate_sender(0), + SIZE_IN => size, + BUSY_OUT => senders_free(0) ); +SERDES1 : serdes4ch + port map( +------------------ +-- CH0 -- + hdinp_ch0 => SFP_RX_P(5), + hdinn_ch0 => SFP_RX_N(5), + hdoutp_ch0 => SFP_TX_P(5), + hdoutn_ch0 => SFP_TX_N(5), + rxiclk_ch0 => sd_rx_clk(0), + txiclk_ch0 => CLK_GPLL_RIGHT, + rx_full_clk_ch0 => sd_rx_clk(0), + rx_half_clk_ch0 => open, + tx_full_clk_ch0 => open, + tx_half_clk_ch0 => open, + fpga_rxrefclk_ch0 => CLK_GPLL_RIGHT, + txdata_ch0 => sd_tx_data(0), + tx_k_ch0 => sd_tx_k(0), + xmit_ch0 => sd_xmit(0), + tx_disp_correct_ch0 => sd_tx_disp(0), + rxdata_ch0 => sd_rx_data(0), + rx_k_ch0 => sd_rx_k(0), + rx_disp_err_ch0 => sd_rx_disp(0), + rx_cv_err_ch0 => sd_cv_err(0), + rx_serdes_rst_ch0_c => sd_rx_serdes_rst(0), + sb_felb_ch0_c => '0', + sb_felb_rst_ch0_c => '0', + tx_pcs_rst_ch0_c => sd_tx_pcs_rst(0), + tx_pwrup_ch0_c => '1', + rx_pcs_rst_ch0_c => sd_rx_pcs_rst(0), + rx_pwrup_ch0_c => '1', + rx_los_low_ch0_s => sd_rx_los(0), + lsm_status_ch0_s => sd_signal_detected(0), + rx_cdr_lol_ch0_s => sd_rx_cdr(0), +-- CH1 -- + hdinp_ch1 => SFP_RX_P(6), + hdinn_ch1 => SFP_RX_N(6), + hdoutp_ch1 => SFP_TX_P(6), + hdoutn_ch1 => SFP_TX_N(6), + rxiclk_ch1 => sd_rx_clk(1), + txiclk_ch1 => CLK_GPLL_RIGHT, + rx_full_clk_ch1 => sd_rx_clk(1), + rx_half_clk_ch1 => open, + tx_full_clk_ch1 => open, + tx_half_clk_ch1 => open, + fpga_rxrefclk_ch1 => CLK_GPLL_RIGHT, + txdata_ch1 => sd_tx_data(1), + tx_k_ch1 => sd_tx_k(1), + xmit_ch1 => sd_xmit(1), + tx_disp_correct_ch1 => sd_tx_disp(1), + rxdata_ch1 => sd_rx_data(1), + rx_k_ch1 => sd_rx_k(1), + rx_disp_err_ch1 => sd_rx_disp(1), + rx_cv_err_ch1 => sd_cv_err(1), + rx_serdes_rst_ch1_c => sd_rx_serdes_rst(1), + sb_felb_ch1_c => '0', + sb_felb_rst_ch1_c => '0', + tx_pcs_rst_ch1_c => sd_tx_pcs_rst(1), + tx_pwrup_ch1_c => '1', + rx_pcs_rst_ch1_c => sd_rx_pcs_rst(1), + rx_pwrup_ch1_c => '1', + rx_los_low_ch1_s => sd_rx_los(1), + lsm_status_ch1_s => sd_signal_detected(1), + rx_cdr_lol_ch1_s => sd_rx_cdr(1), +-- CH2 -- + hdinp_ch2 => SFP_RX_P(7), + hdinn_ch2 => SFP_RX_N(7), + hdoutp_ch2 => SFP_TX_P(7), + hdoutn_ch2 => SFP_TX_N(7), + rxiclk_ch2 => sd_rx_clk(2), + txiclk_ch2 => CLK_GPLL_RIGHT, + rx_full_clk_ch2 => sd_rx_clk(2), + rx_half_clk_ch2 => open, + tx_full_clk_ch2 => open, + tx_half_clk_ch2 => open, + fpga_rxrefclk_ch2 => CLK_GPLL_RIGHT, + txdata_ch2 => sd_tx_data(2), + tx_k_ch2 => sd_tx_k(2), + xmit_ch2 => sd_xmit(2), + tx_disp_correct_ch2 => sd_tx_disp(2), + rxdata_ch2 => sd_rx_data(2), + rx_k_ch2 => sd_rx_k(2), + rx_disp_err_ch2 => sd_rx_disp(2), + rx_cv_err_ch2 => sd_cv_err(2), + rx_serdes_rst_ch2_c => sd_rx_serdes_rst(2), + sb_felb_ch2_c => '0', + sb_felb_rst_ch2_c => '0', + tx_pcs_rst_ch2_c => sd_tx_pcs_rst(2), + tx_pwrup_ch2_c => '1', + rx_pcs_rst_ch2_c => sd_rx_pcs_rst(2), + rx_pwrup_ch2_c => '1', + rx_los_low_ch2_s => sd_rx_los(2), + lsm_status_ch2_s => sd_signal_detected(2), + rx_cdr_lol_ch2_s => sd_rx_cdr(2), +-- CH3 -- + hdinp_ch3 => SFP_RX_P(8), + hdinn_ch3 => SFP_RX_N(8), + hdoutp_ch3 => SFP_TX_P(8), + hdoutn_ch3 => SFP_TX_N(8), + rxiclk_ch3 => sd_rx_clk(3), + txiclk_ch3 => CLK_GPLL_RIGHT, + rx_full_clk_ch3 => sd_rx_clk(3), + rx_half_clk_ch3 => open, + tx_full_clk_ch3 => open, + tx_half_clk_ch3 => open, + fpga_rxrefclk_ch3 => CLK_GPLL_RIGHT, + txdata_ch3 => sd_tx_data(3), + tx_k_ch3 => sd_tx_k(3), + xmit_ch3 => sd_xmit(3), + tx_disp_correct_ch3 => sd_tx_disp(3), + rxdata_ch3 => sd_rx_data(3), + rx_k_ch3 => sd_rx_k(3), + rx_disp_err_ch3 => sd_rx_disp(3), + rx_cv_err_ch3 => sd_cv_err(3), + rx_serdes_rst_ch3_c => sd_rx_serdes_rst(3), + sb_felb_ch3_c => '0', + sb_felb_rst_ch3_c => '0', + tx_pcs_rst_ch3_c => sd_tx_pcs_rst(3), + tx_pwrup_ch3_c => '1', + rx_pcs_rst_ch3_c => sd_rx_pcs_rst(3), + rx_pwrup_ch3_c => '1', + rx_los_low_ch3_s => sd_rx_los(3), + lsm_status_ch3_s => sd_signal_detected(3), + rx_cdr_lol_ch3_s => sd_rx_cdr(3), +---- Miscillaneous ports + fpga_txrefclk => CLK_GPLL_RIGHT, + tx_serdes_rst_c => '0', + tx_pll_lol_qd_s => sd_tx_pll_lol, + tx_sync_qd_c => '0', + rst_qd_c => sd1_quad_rst, + serdes_rst_qd_c => '0' + ); + + +sd1_quad_rst <= or_all(sd_quad_rst); + + + +senders_free(1) <= '0'; +senders_free(2) <= '0'; + SFP_TXDIS(4 downto 1) <= (others => '1'); SFP_TXDIS(8 downto 6) <= (others => '1'); diff --git a/trb_net16_gbe_main_control.vhd b/trb_net16_gbe_main_control.vhd index 30bb2b8..7b1e4e1 100644 --- a/trb_net16_gbe_main_control.vhd +++ b/trb_net16_gbe_main_control.vhd @@ -73,6 +73,12 @@ port ( -- signals to/from hub MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); + CNT_GENERATE_PACKET_IN : in std_logic; + CNT_TIMESTAMP_IN : in std_logic_vector(31 downto 0); + CNT_DEST_ADDR_IN : in std_logic_vector(15 downto 0); + CNT_SIZE_IN : in std_logic_vector(15 downto 0); + CNT_BUSY_OUT : out std_logic; + GSC_CLK_IN : in std_logic; GSC_INIT_DATAREADY_OUT : out std_logic; GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); @@ -218,6 +224,11 @@ port map( DHCP_START_IN => dhcp_start, DHCP_DONE_OUT => dhcp_done, + CNT_GENERATE_PACKET_IN => CNT_GENERATE_PACKET_IN, + CNT_TIMESTAMP_IN => CNT_TIMESTAMP_IN, + CNT_DEST_ADDR_IN => CNT_DEST_ADDR_IN, + CNT_SIZE_IN => CNT_SIZE_IN, + GSC_CLK_IN => GSC_CLK_IN, GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, @@ -452,6 +463,7 @@ end process FLOW_MACHINE; TC_TRANSMIT_DATA_OUT <= '1' when (flow_current_state = TRANSMIT_DATA) else '0'; TC_TRANSMIT_CTRL_OUT <= '1' when (flow_current_state = TRANSMIT_CTRL) else '0'; +CNT_BUSY_OUT <= '0' when flow_current_state = IDLE else '1'; --*********************** -- LINK STATE CONTROL diff --git a/trb_net16_gbe_protocol_selector.vhd b/trb_net16_gbe_protocol_selector.vhd index 04e4264..d2e9b23 100644 --- a/trb_net16_gbe_protocol_selector.vhd +++ b/trb_net16_gbe_protocol_selector.vhd @@ -73,6 +73,11 @@ port ( GSC_REPLY_READ_OUT : out std_logic; GSC_BUSY_IN : in std_logic; + CNT_GENERATE_PACKET_IN : in std_logic; + CNT_TIMESTAMP_IN : in std_logic_vector(31 downto 0); + CNT_DEST_ADDR_IN : in std_logic_vector(15 downto 0); + CNT_SIZE_IN : in std_logic_vector(15 downto 0); + -- input for statistics from outside STAT_DATA_IN : in std_logic_vector(31 downto 0); STAT_ADDR_IN : in std_logic_vector(7 downto 0); @@ -158,9 +163,10 @@ port map ( SENT_FRAMES_OUT => SENT_FRAMES_OUT(1 * 16 - 1 downto 0 * 16), -- END OF INTERFACE - TIMESTAMP_IN => (others => '0'), - DEST_ADDR_IN => (others => '0'), - GENERATE_PACKET_IN => '0', + TIMESTAMP_IN => CNT_TIMESTAMP_IN, + DEST_ADDR_IN => CNT_DEST_ADDR_IN, + SIZE_IN => CNT_SIZE_IN, + GENERATE_PACKET_IN => CNT_GENERATE_PACKET_IN, DEBUG_OUT => PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32) ); diff --git a/trb_net16_gbe_response_constructor_CNTeseter.vhd b/trb_net16_gbe_response_constructor_CNTeseter.vhd index cb8fec7..be15c93 100644 --- a/trb_net16_gbe_response_constructor_CNTeseter.vhd +++ b/trb_net16_gbe_response_constructor_CNTeseter.vhd @@ -59,6 +59,7 @@ port ( TIMESTAMP_IN : in std_logic_vector(31 downto 0); DEST_ADDR_IN : in std_logic_vector(15 downto 0); + SIZE_IN : in std_logic_vector(15 downto 0); GENERATE_PACKET_IN : in std_logic; -- debug @@ -77,31 +78,11 @@ attribute syn_encoding of construct_current_state: signal is "safe,gray"; signal load_ctr : integer range 0 to 255; signal tc_data : std_logic_vector(8 downto 0); -signal timer : unsigned(28 downto 0); -signal timer_lock : std_logic; signal timer_t : std_logic_vector(7 downto 0); signal state : std_logic_vector(3 downto 0); begin -TIMER_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - timer <= (others => '0'); - timer_lock <= '0'; - elsif (timer(15) = '0') then - timer_lock <= '0'; - timer <= timer + 1; - elsif (timer(15) = '1') then - timer_lock <= '1'; - timer <= timer + 1; - else - timer <= timer + 1; - end if; - end if; -end process TIMER_PROC; - CONSTRUCT_MACHINE_PROC : process(CLK) begin if rising_edge(CLK) then @@ -113,14 +94,13 @@ begin end if; end process CONSTRUCT_MACHINE_PROC; -CONSTRUCT_MACHINE : process(construct_current_state, GENERATE_PACKET_IN, TC_BUSY_IN, PS_SELECTED_IN, load_ctr, timer, timer_lock) +CONSTRUCT_MACHINE : process(construct_current_state, GENERATE_PACKET_IN, TC_BUSY_IN, PS_SELECTED_IN, load_ctr) begin case construct_current_state is when IDLE => state <= x"1"; - --if (GENERATE_PACKET_IN = '1') then - if (timer(15) = '1' and timer_lock = '0') then + if (GENERATE_PACKET_IN = '1') then construct_next_state <= WAIT_FOR_LOAD; else construct_next_state <= IDLE; diff --git a/trb_net16_med_ecp_sfp_gbe_8b.vhd b/trb_net16_med_ecp_sfp_gbe_8b.vhd index 8c76285..ae46d42 100644 --- a/trb_net16_med_ecp_sfp_gbe_8b.vhd +++ b/trb_net16_med_ecp_sfp_gbe_8b.vhd @@ -32,16 +32,7 @@ port( FT_RXD_OUT : out std_logic_vector(7 downto 0); FT_RX_EN_OUT : out std_logic; FT_RX_ER_OUT : out std_logic; - --SFP Connection - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_REFCLK_P_IN : in std_logic; - SD_REFCLK_N_IN : in std_logic; - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic; -- SFP disable + -- Autonegotiation stuff MR_RESET_IN : in std_logic; MR_MODE_IN : in std_logic; @@ -51,184 +42,31 @@ port( MR_AN_COMPLETE_OUT : out std_logic; MR_AN_ENABLE_IN : in std_logic; MR_RESTART_AN_IN : in std_logic; - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) + + SD_RX_CLK_IN : in std_logic; + SD_TX_DATA_OUT : out std_logic_vector(7 downto 0); + SD_TX_KCNTL_OUT : out std_logic; + SD_TX_CORRECT_DISP_OUT : out std_logic; + SD_RX_DATA_IN : in std_logic_vector(7 downto 0); + SD_RX_KCNTL_IN : in std_logic; + SD_RX_DISP_ERROR_IN : in std_logic; + SD_RX_CV_ERROR_IN : in std_logic; + SD_RX_SERDES_RST_OUT : out std_logic; + SD_RX_PCS_RST_OUT : out std_logic; + SD_TX_PCS_RST_OUT : out std_logic; + SD_RX_LOS_IN : in std_logic; + SD_SIGNAL_DETECTED_IN : in std_logic; + SD_RX_CDR_IN : in std_logic; + SD_TX_PLL_LOL_IN : in std_logic; + SD_QUAD_RST_OUT : out std_logic ); end entity; architecture trb_net16_med_ecp_sfp_gbe_8b of trb_net16_med_ecp_sfp_gbe_8b is --- Placer Directives ---attribute HGROUP : string; --- for whole architecture ---attribute HGROUP of trb_net16_med_ecp_sfp_gbe_8b : architecture is "media_interface_group"; attribute syn_sharing : string; attribute syn_sharing of trb_net16_med_ecp_sfp_gbe_8b : architecture is "off"; -component serdes_gbe_0ch is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0ch.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - rxiclk_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (7 downto 0); - tx_k_ch0 : in std_logic; - xmit_ch0 : in std_logic; - tx_disp_correct_ch0 : in std_logic; - rxdata_ch0 : out std_logic_vector (7 downto 0); - rx_k_ch0 : out std_logic; - rx_disp_err_ch0 : out std_logic; - rx_cv_err_ch0 : out std_logic; - rx_serdes_rst_ch0_c : in std_logic; - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pcs_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pcs_rst_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - serdes_rst_qd_c : in std_logic); - -end component; - -component serdes_gbe_0_extclock_8b is -GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt"); -port( refclkp : in std_logic; - refclkn : in std_logic; - hdinp0 : in std_logic; - hdinn0 : in std_logic; - hdoutp0 : out std_logic; - hdoutn0 : out std_logic; - ff_rxiclk_ch0 : in std_logic; - ff_txiclk_ch0 : in std_logic; - ff_ebrd_clk_0 : in std_logic; - ff_txdata_ch0 : in std_logic_vector (7 downto 0); - ff_rxdata_ch0 : out std_logic_vector (7 downto 0); - ff_tx_k_cntrl_ch0 : in std_logic; - ff_rx_k_cntrl_ch0 : out std_logic; - ff_rxfullclk_ch0 : out std_logic; - ff_xmit_ch0 : in std_logic; - ff_correct_disp_ch0 : in std_logic; - ff_disp_err_ch0 : out std_logic; - ff_cv_ch0 : out std_logic; - ff_rx_even_ch0 : out std_logic; - ffc_rrst_ch0 : in std_logic; - ffc_lane_tx_rst_ch0 : in std_logic; - ffc_lane_rx_rst_ch0 : in std_logic; - ffc_txpwdnb_ch0 : in std_logic; - ffc_rxpwdnb_ch0 : in std_logic; - ffs_rlos_lo_ch0 : out std_logic; - ffs_ls_sync_status_ch0 : out std_logic; - ffs_rlol_ch0 : out std_logic; - oob_out_ch0 : out std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - ff_txfullclk : out std_logic; - ff_txhalfclk : out std_logic; - refck2core : out std_logic; - ffs_plol : out std_logic - ); -end component; - -component serdes_gbe_0_intclock_8b is - GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt"); - port ( - core_txrefclk : in std_logic; - core_rxrefclk : in std_logic; - hdinp0, hdinn0 : in std_logic; - hdoutp0, hdoutn0 : out std_logic; - ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; - ff_txdata_ch0 : in std_logic_vector (7 downto 0); - ff_rxdata_ch0 : out std_logic_vector (7 downto 0); - ff_tx_k_cntrl_ch0 : in std_logic; - ff_rx_k_cntrl_ch0 : out std_logic; - ff_rxfullclk_ch0 : out std_logic; - ff_xmit_ch0 : in std_logic; - ff_correct_disp_ch0 : in std_logic; - ff_disp_err_ch0, ff_cv_ch0 : out std_logic; - ff_rx_even_ch0 : out std_logic; - ffc_rrst_ch0 : in std_logic; - ffc_lane_tx_rst_ch0 : in std_logic; - ffc_lane_rx_rst_ch0 : in std_logic; - ffc_txpwdnb_ch0 : in std_logic; - ffc_rxpwdnb_ch0 : in std_logic; - ffs_rlos_lo_ch0 : out std_logic; - ffs_ls_sync_status_ch0 : out std_logic; - ffs_rlol_ch0 : out std_logic; - oob_out_ch0 : out std_logic; - ffc_macro_rst : in std_logic; - ffc_quad_rst : in std_logic; - ffc_trst : in std_logic; - ff_txfullclk : out std_logic; - ff_txhalfclk : out std_logic; - ffs_plol : out std_logic); - -end component; - --- component sgmii_gbe_pcs34 --- port( rst_n : in std_logic; --- signal_detect : in std_logic; --- gbe_mode : in std_logic; --- sgmii_mode : in std_logic; --- operational_rate : in std_logic_vector(1 downto 0); --- debug_link_timer_short : in std_logic; --- rx_compensation_err : out std_logic; --- tx_clk_125 : in std_logic; --- tx_clock_enable_source : out std_logic; --- tx_clock_enable_sink : in std_logic; --- tx_d : in std_logic_vector(7 downto 0); --- tx_en : in std_logic; --- tx_er : in std_logic; --- rx_clk_125 : in std_logic; --- rx_clock_enable_source : out std_logic; --- rx_clock_enable_sink : in std_logic; --- rx_d : out std_logic_vector(7 downto 0); --- rx_dv : out std_logic; --- rx_er : out std_logic; --- col : out std_logic; --- crs : out std_logic; --- tx_data : out std_logic_vector(7 downto 0); --- tx_kcntl : out std_logic; --- tx_disparity_cntl : out std_logic; --- serdes_recovered_clk : in std_logic; --- rx_data : in std_logic_vector(7 downto 0); --- rx_even : in std_logic; --- rx_kcntl : in std_logic; --- rx_disp_err : in std_logic; --- rx_cv_err : in std_logic; --- rx_err_decode_mode : in std_logic; --- mr_an_complete : out std_logic; --- mr_page_rx : out std_logic; --- mr_lp_adv_ability : out std_logic_vector(15 downto 0); --- mr_main_reset : in std_logic; --- mr_an_enable : in std_logic; --- mr_restart_an : in std_logic; --- mr_adv_ability : in std_logic_vector(15 downto 0) --- ); --- end component; - component sgmii_gbe_pcs34 port( rst_n : in std_logic; signal_detect : in std_logic; @@ -481,257 +319,26 @@ signal mr_lp_adv_ability, mr_adv_ability : std_logic_vector(15 downto 0); begin --- Reset state machine for SerDes --- THE_RESET_STATEMACHINE: trb_net16_lsm_sfp_gbe --- port map( --- SYSCLK => CLK_125_IN, --- RESET => '0', -- really? --- CLEAR => RESET, -- from 100MHz PLL, includes async part --- -- status signals --- SFP_MISSING_IN => SD_PRSNT_N_IN, --- SFP_LOS_IN => SD_LOS_IN, --- SD_LINK_OK_IN => '1', -- not used --- SD_LOS_IN => '0', -- not used --- SD_TXCLK_BAD_IN => sd_link_error(2), -- plol --- SD_RXCLK_BAD_IN => sd_link_error(1), -- rlol --- -- control signals --- FULL_RESET_OUT => quad_rst, --- LANE_RESET_OUT => lane_rst, --- USER_RESET_OUT => user_rst, --- -- debug signals --- TIMING_CTR_OUT => open, --- BSM_OUT => reset_bsm, --- DEBUG_OUT => reset_debug --- ); - --- gk 28.04.10 --- SerDes for GbE -clk_int : if (USE_125MHZ_EXTCLK = 0) generate - refclkcore <= CLK_125_IN; --sd_tx_clk; --CLK_125_IN; --- SERDES_GBE : serdes_gbe_0_intclock_8b --- port map( --- core_txrefclk => CLK_125_IN, --- core_rxrefclk => CLK_125_IN, --- hdinp0 => SD_RXD_P_IN, --- hdinn0 => SD_RXD_N_IN, --- hdoutp0 => SD_TXD_P_OUT, --- hdoutn0 => SD_TXD_N_OUT, --- ff_rxiclk_ch0 => sd_rx_clk, --- ff_txiclk_ch0 => sd_tx_clk, --- ff_ebrd_clk_0 => sd_rx_clk, --- ff_txdata_ch0 => sd_tx_data, --- ff_rxdata_ch0 => sd_rx_data, --- ff_tx_k_cntrl_ch0 => sd_tx_kcntl, --- ff_rx_k_cntrl_ch0 => sd_rx_kcntl, --- ff_rxfullclk_ch0 => sd_rx_clk, --- ff_xmit_ch0 => '0', --- ff_correct_disp_ch0 => sd_tx_correct_disp, --- ff_disp_err_ch0 => sd_rx_disp_error, --- ff_cv_ch0 => sd_rx_cv_error, --- ff_rx_even_ch0 => sd_rx_even, --- ffc_rrst_ch0 => '0', --- ffc_lane_tx_rst_ch0 => lane_rst, --- ffc_lane_rx_rst_ch0 => lane_rst, --- ffc_txpwdnb_ch0 => '1', --- ffc_rxpwdnb_ch0 => '1', --- ffs_rlos_lo_ch0 => sd_link_error(0), --- ffs_ls_sync_status_ch0 => sd_link_ok, --- ffs_rlol_ch0 => sd_link_error(1), --- oob_out_ch0 => open, --- ffc_macro_rst => '0', --- ffc_quad_rst => quad_rst, --- ffc_trst => '0', --- ff_txfullclk => sd_tx_clk, --- ff_txhalfclk => open, --- ffs_plol => sd_link_error(2) --- ); - - SERDES_GBE : serdes_gbe_0ch - port map( - ------------------ - -- CH0 -- - hdinp_ch0 => SD_RXD_P_IN, - hdinn_ch0 => SD_RXD_N_IN, - hdoutp_ch0 => SD_TXD_P_OUT, - hdoutn_ch0 => SD_TXD_N_OUT, - rxiclk_ch0 => sd_rx_clk, - txiclk_ch0 => CLK_125_IN, --sd_tx_clk, - rx_full_clk_ch0 => sd_rx_clk, - rx_half_clk_ch0 => open, - tx_full_clk_ch0 => open, --sd_tx_clk, - tx_half_clk_ch0 => open, - fpga_rxrefclk_ch0 => CLK_125_IN, - txdata_ch0 => sd_tx_data_q, - tx_k_ch0 => sd_tx_kcntl_q, - xmit_ch0 => xmit, --'0', - tx_disp_correct_ch0 => sd_tx_correct_disp_q, - rxdata_ch0 => sd_rx_data, - rx_k_ch0 => sd_rx_kcntl, - rx_disp_err_ch0 => sd_rx_disp_error, - rx_cv_err_ch0 => sd_rx_cv_error, - rx_serdes_rst_ch0_c => rx_serdes_rst, - sb_felb_ch0_c => '0', - sb_felb_rst_ch0_c => '0', - tx_pcs_rst_ch0_c => tx_pcs_rst, - tx_pwrup_ch0_c => '1', - rx_pcs_rst_ch0_c => rx_pcs_rst, - rx_pwrup_ch0_c => '1', - rx_los_low_ch0_s => los, - lsm_status_ch0_s => signal_detected, - rx_cdr_lol_ch0_s => rx_cdr_lol, - -- CH1 -- - -- CH2 -- - -- CH3 -- - ---- Miscillaneous ports - fpga_txrefclk => CLK_125_IN, - tx_serdes_rst_c => '0', - tx_pll_lol_qd_s => tx_pll_lol, - rst_qd_c => quad_rst, - serdes_rst_qd_c => '0' - ); - -end generate clk_int; - -clk_ext : if (USE_125MHZ_EXTCLK = 1) generate - SERDES_GBE : serdes_gbe_0_extclock_8b - port map( -- SerDes connection to outside world - refclkp => SD_REFCLK_P_IN, -- SerDes REFCLK diff. input - refclkn => SD_REFCLK_N_IN, - hdinp0 => SD_RXD_P_IN, -- SerDes RX diff. input - hdinn0 => SD_RXD_N_IN, - hdoutp0 => SD_TXD_P_OUT, -- SerDes TX diff. output - hdoutn0 => SD_TXD_N_OUT, - refck2core => refclkcore, -- reference clock from input - -- RX part - ff_rxfullclk_ch0 => sd_rx_clk, -- RX full clock output - ff_rxiclk_ch0 => sd_rx_clk, - ff_ebrd_clk_0 => sd_rx_clk, -- EB ist not used as recommended by Lattice - ff_rxdata_ch0 => sd_rx_data, -- RX data output - ff_rx_k_cntrl_ch0 => sd_rx_kcntl, -- RX komma output - ff_rx_even_ch0 => sd_rx_even, -- for autonegotiation (output) - ff_disp_err_ch0 => sd_rx_disp_error, -- RX disparity error - ff_cv_ch0 => sd_rx_cv_error, -- RX code violation error - -- TX part - ff_txfullclk => sd_tx_clk, -- TX full clock output - ff_txiclk_ch0 => sd_tx_clk, - ff_txhalfclk => open, - ff_txdata_ch0 => sd_tx_data, -- TX data input - ff_tx_k_cntrl_ch0 => sd_tx_kcntl, -- TX komma input - ff_xmit_ch0 => '0', -- for autonegotiation (input) - ff_correct_disp_ch0 => sd_tx_correct_disp, -- controls disparity at IPG start (input) - -- Resets and power down - ffc_quad_rst => quad_rst, -- async reset for whole QUAD (active high) - ffc_lane_tx_rst_ch0 => lane_rst, -- async reset for TX channel - ffc_lane_rx_rst_ch0 => lane_rst, -- async reset for RX channel - ffc_rrst_ch0 => '0', -- '0' for normal operation - ffc_macro_rst => '0', -- '0' for normal operation - ffc_trst => '0', -- '0' for normal operation - ffc_txpwdnb_ch0 => '1', -- must be '1' - ffc_rxpwdnb_ch0 => '1', -- must be '1' - -- Status outputs - ffs_ls_sync_status_ch0 => sd_link_ok, -- synced to kommas? - ffs_rlos_lo_ch0 => sd_link_error(0), -- loss of signal in RX channel - ffs_rlol_ch0 => sd_link_error(1), -- loss of lock in RX PLL - ffs_plol => sd_link_error(2), -- loss of lock in TX PLL - oob_out_ch0 => open -- not needed - ); -end generate clk_ext; - ---SD_RX_DATA_PROC: process( sd_rx_clk ) ---begin --- if( rising_edge(sd_rx_clk) ) then --- sd_rx_debug(15 downto 12) <= (others => '0'); --- sd_rx_debug(11) <= sd_rx_disp_error; --- sd_rx_debug(10) <= sd_rx_even; --- sd_rx_debug(9) <= sd_rx_cv_error; --- sd_rx_debug(8) <= sd_rx_kcntl; --- sd_rx_debug(7 downto 0) <= sd_rx_data; --- end if; ---end process SD_RX_DATA_PROC; --- ---SD_TX_DATA_PROC: process( CLK_125_IN) --sd_tx_clk ) ---begin --- if( rising_edge(CLK_125_IN)) then --sd_tx_clk) ) then --- sd_tx_debug(15 downto 10) <= (others => '0'); --- sd_tx_debug(9) <= sd_tx_correct_disp; --- sd_tx_debug(8) <= sd_tx_kcntl; --- sd_tx_debug(7 downto 0) <= sd_tx_data; --- end if; ---end process SD_TX_DATA_PROC; - -buf_stat_debug(63 downto 40) <= (others => '0'); -buf_stat_debug(39 downto 36) <= reset_debug(3 downto 0); -buf_stat_debug(35 downto 32) <= reset_bsm; --- logic analyzer signals -buf_stat_debug(31) <= pcs_mr_page_rx; -buf_stat_debug(30) <= pcs_mr_reset; --pcs_mr_an_complete; -buf_stat_debug(28 downto 26) <= reset_bsm(2 downto 0); -buf_stat_debug(25 downto 23) <= sd_link_error(2 downto 0); -buf_stat_debug(22) <= sd_link_ok; -buf_stat_debug(21 downto 12) <= sd_tx_debug(9 downto 0); -buf_stat_debug(11 downto 0) <= sd_rx_debug(11 downto 0); - - ---SGMII_GBE_PCS : sgmii33 port map ( --- rst_n => GSR_N, --- signal_detect => signal_detected, --- gbe_mode => '1', --- sgmii_mode => '0', --- operational_rate => operational_rate, --- debug_link_timer_short => '0', --- rx_compensation_err => compensation_err, --- tx_clk_125 => CLK_125_IN, --- tx_clock_enable_source => tx_clk_en, --- tx_clock_enable_sink => tx_clk_en, --- tx_d => FT_TXD_IN, --pcs_rxd, --pcs_txd, --- tx_en => FT_TX_EN_IN, --pcs_rx_dv, --pcs_tx_en, --- tx_er => FT_TX_ER_IN, --pcs_rx_er, --pcs_tx_er, --- rx_clk_125 => CLK_125_IN, --- rx_clock_enable_source => rx_clk_en, --- rx_clock_enable_sink => rx_clk_en, --- rx_d => pcs_rx_d, --- rx_dv => pcs_rx_dv, --- rx_er => pcs_rx_er, --- col => FT_COL_OUT, --- crs => FT_CRS_OUT, --- tx_data => sd_tx_data, --- tx_kcntl => sd_tx_kcntl, --- tx_disparity_cntl => sd_tx_correct_disp, --- serdes_recovered_clk => sd_rx_clk, --- rx_data => sd_rx_data_q, --- rx_even => '0', --- rx_kcntl => sd_rx_kcntl_q, --- rx_disp_err => sd_rx_disp_error_q, --- rx_cv_err => sd_rx_cv_error_q, --- rx_err_decode_mode => '0', --- mr_an_complete => an_complete, --- mr_page_rx => mr_page_rx, --- mr_lp_adv_ability => mr_lp_adv_ability, --- mr_main_reset => mr_main_reset, --reset_i, --- mr_an_enable => '1', --'1', --- mr_restart_an => mr_restart_an, --- mr_adv_ability => mr_adv_ability --x"0020" --- ); SYNC_TX_PROC : process(CLK_125_IN) begin if rising_edge(CLK_125_IN) then - sd_tx_data_q <= sd_tx_data; - sd_tx_kcntl_q <= sd_tx_kcntl; - sd_tx_correct_disp_q <= sd_tx_correct_disp; + SD_TX_DATA_OUT <= sd_tx_data; + SD_TX_KCNTL_OUT <= sd_tx_kcntl; + SD_TX_CORRECT_DISP_OUT <= sd_tx_correct_disp; end if; end process SYNC_TX_PROC; - SYNC_RX_PROC : process(sd_rx_clk) + SYNC_RX_PROC : process(SD_RX_CLK_IN) begin - if rising_edge(sd_rx_clk) then - sd_rx_data_q <= sd_rx_data; - sd_rx_kcntl_q <= sd_rx_kcntl; - sd_rx_disp_error_q <= sd_rx_disp_error; - sd_rx_cv_error_q <= sd_rx_cv_error; + if rising_edge(SD_RX_CLK_IN) then + sd_rx_data_q <= SD_RX_DATA_IN; + sd_rx_kcntl_q <= SD_RX_KCNTL_IN; + sd_rx_disp_error_q <= SD_RX_DISP_ERROR_IN; + sd_rx_cv_error_q <= SD_RX_CV_ERROR_IN; end if; end process SYNC_RX_PROC; @@ -741,7 +348,7 @@ buf_stat_debug(11 downto 0) <= sd_rx_debug(11 downto 0); SGMII_GBE_PCS : sgmii_gbe_pcs34 port map( rst_n => GSR_N, - signal_detect => signal_detected, + signal_detect => SD_SIGNAL_DETECTED_IN, gbe_mode => '1', sgmii_mode => '0', operational_rate => operational_rate, @@ -779,7 +386,7 @@ buf_stat_debug(11 downto 0) <= sd_rx_debug(11 downto 0); xmit_autoneg => xmit, - serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream + serdes_recovered_clk => SD_RX_CLK_IN, -- 125MHz recovered from receive bit stream rx_data => sd_rx_data_q, -- RX data from SerDes rx_kcntl => sd_rx_kcntl_q, -- RX komma control from SerDes rx_err_decode_mode => '0', -- receive error control mode fixed to normal @@ -810,18 +417,18 @@ rst_n <= not RESET; u0_reset_controller_pcs : reset_controller_pcs port map( rst_n => rst_n, clk => CLK_125_IN, - tx_plol => tx_pll_lol, - rx_cdr_lol => rx_cdr_lol, - quad_rst_out => quad_rst, - tx_pcs_rst_out => tx_pcs_rst, - rx_pcs_rst_out => rx_pcs_rst + tx_plol => SD_TX_PLL_LOL_IN, + rx_cdr_lol => SD_RX_CDR_IN, + quad_rst_out => SD_QUAD_RST_OUT, + tx_pcs_rst_out => SD_TX_PCS_RST_OUT, + rx_pcs_rst_out => SD_RX_PCS_RST_OUT ); u0_reset_controller_cdr : reset_controller_cdr port map( rst_n => rst_n, clk => CLK_125_IN, - cdr_lol => rx_cdr_lol, - cdr_rst_out => rx_serdes_rst + cdr_lol => SD_RX_CDR_IN, + cdr_rst_out => SD_RX_SERDES_RST_OUT ); u0_rate_resolution : rate_resolution port map( @@ -876,11 +483,7 @@ MR_AN_PAGE_RX_OUT <= pcs_mr_page_rx; -- Clock games CLK_125_OUT <= CLK_125_IN; --sd_tx_clk; -CLK_125_RX_OUT <= sd_rx_clk; +CLK_125_RX_OUT <= SD_RX_CLK_IN; --- Fakes -STAT_OP <= (others => '0'); -SD_TXDIS_OUT <= '0'; -- enable -STAT_DEBUG <= buf_stat_debug; end architecture; \ No newline at end of file diff --git a/trb_net_gbe_components.vhd b/trb_net_gbe_components.vhd index 4fab2a0..08408d6 100644 --- a/trb_net_gbe_components.vhd +++ b/trb_net_gbe_components.vhd @@ -9,6 +9,132 @@ use work.trb_net_gbe_protocols.all; package trb_net_gbe_components is +component serdes4ch is + GENERIC (USER_CONFIG_FILE : String := "serdes4ch.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (7 downto 0); + tx_k_ch0 : in std_logic; + xmit_ch0 : in std_logic; + tx_disp_correct_ch0 : in std_logic; + rxdata_ch0 : out std_logic_vector (7 downto 0); + rx_k_ch0 : out std_logic; + rx_disp_err_ch0 : out std_logic; + rx_cv_err_ch0 : out std_logic; + rx_serdes_rst_ch0_c : in std_logic; + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pcs_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pcs_rst_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; +-- CH1 -- + hdinp_ch1, hdinn_ch1 : in std_logic; + hdoutp_ch1, hdoutn_ch1 : out std_logic; + rxiclk_ch1 : in std_logic; + txiclk_ch1 : in std_logic; + rx_full_clk_ch1 : out std_logic; + rx_half_clk_ch1 : out std_logic; + tx_full_clk_ch1 : out std_logic; + tx_half_clk_ch1 : out std_logic; + fpga_rxrefclk_ch1 : in std_logic; + txdata_ch1 : in std_logic_vector (7 downto 0); + tx_k_ch1 : in std_logic; + xmit_ch1 : in std_logic; + tx_disp_correct_ch1 : in std_logic; + rxdata_ch1 : out std_logic_vector (7 downto 0); + rx_k_ch1 : out std_logic; + rx_disp_err_ch1 : out std_logic; + rx_cv_err_ch1 : out std_logic; + rx_serdes_rst_ch1_c : in std_logic; + sb_felb_ch1_c : in std_logic; + sb_felb_rst_ch1_c : in std_logic; + tx_pcs_rst_ch1_c : in std_logic; + tx_pwrup_ch1_c : in std_logic; + rx_pcs_rst_ch1_c : in std_logic; + rx_pwrup_ch1_c : in std_logic; + rx_los_low_ch1_s : out std_logic; + lsm_status_ch1_s : out std_logic; + rx_cdr_lol_ch1_s : out std_logic; +-- CH2 -- + hdinp_ch2, hdinn_ch2 : in std_logic; + hdoutp_ch2, hdoutn_ch2 : out std_logic; + rxiclk_ch2 : in std_logic; + txiclk_ch2 : in std_logic; + rx_full_clk_ch2 : out std_logic; + rx_half_clk_ch2 : out std_logic; + tx_full_clk_ch2 : out std_logic; + tx_half_clk_ch2 : out std_logic; + fpga_rxrefclk_ch2 : in std_logic; + txdata_ch2 : in std_logic_vector (7 downto 0); + tx_k_ch2 : in std_logic; + xmit_ch2 : in std_logic; + tx_disp_correct_ch2 : in std_logic; + rxdata_ch2 : out std_logic_vector (7 downto 0); + rx_k_ch2 : out std_logic; + rx_disp_err_ch2 : out std_logic; + rx_cv_err_ch2 : out std_logic; + rx_serdes_rst_ch2_c : in std_logic; + sb_felb_ch2_c : in std_logic; + sb_felb_rst_ch2_c : in std_logic; + tx_pcs_rst_ch2_c : in std_logic; + tx_pwrup_ch2_c : in std_logic; + rx_pcs_rst_ch2_c : in std_logic; + rx_pwrup_ch2_c : in std_logic; + rx_los_low_ch2_s : out std_logic; + lsm_status_ch2_s : out std_logic; + rx_cdr_lol_ch2_s : out std_logic; +-- CH3 -- + hdinp_ch3, hdinn_ch3 : in std_logic; + hdoutp_ch3, hdoutn_ch3 : out std_logic; + rxiclk_ch3 : in std_logic; + txiclk_ch3 : in std_logic; + rx_full_clk_ch3 : out std_logic; + rx_half_clk_ch3 : out std_logic; + tx_full_clk_ch3 : out std_logic; + tx_half_clk_ch3 : out std_logic; + fpga_rxrefclk_ch3 : in std_logic; + txdata_ch3 : in std_logic_vector (7 downto 0); + tx_k_ch3 : in std_logic; + xmit_ch3 : in std_logic; + tx_disp_correct_ch3 : in std_logic; + rxdata_ch3 : out std_logic_vector (7 downto 0); + rx_k_ch3 : out std_logic; + rx_disp_err_ch3 : out std_logic; + rx_cv_err_ch3 : out std_logic; + rx_serdes_rst_ch3_c : in std_logic; + sb_felb_ch3_c : in std_logic; + sb_felb_rst_ch3_c : in std_logic; + tx_pcs_rst_ch3_c : in std_logic; + tx_pwrup_ch3_c : in std_logic; + rx_pcs_rst_ch3_c : in std_logic; + rx_pwrup_ch3_c : in std_logic; + rx_los_low_ch3_s : out std_logic; + lsm_status_ch3_s : out std_logic; + rx_cdr_lol_ch3_s : out std_logic; +---- Miscillaneous ports + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + tx_sync_qd_c : in std_logic; + rst_qd_c : in std_logic; + serdes_rst_qd_c : in std_logic); + +end component; + component CNTester_Main is port ( CLKSYS_IN : in std_logic; @@ -16,7 +142,10 @@ component CNTester_Main is GENERATE_OUT : out std_logic_vector(2 downto 0); TIMESTAMP_OUT : out std_logic_vector(31 downto 0); - DEST_ADDR_OUT : out std_logic_vector(15 downto 0) + DEST_ADDR_OUT : out std_logic_vector(15 downto 0); + SIZE_OUT : out std_logic_vector(15 downto 0); + + SENDERS_FREE_IN : in std_logic_vector(2 downto 0) ); end component; @@ -27,32 +156,40 @@ component CNTester_module is RESET : in std_logic; GSR_N : in std_logic; - SFP_RXD_P_IN : in std_logic; - SFP_RXD_N_IN : in std_logic; - SFP_TXD_P_OUT : out std_logic; - SFP_TXD_N_OUT : out std_logic; - SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SFP_TXDIS_OUT : out std_logic; -- SFP disable + -- serdes io + SD_RX_CLK_IN : in std_logic; + SD_TX_DATA_OUT : out std_logic_vector(7 downto 0); + SD_TX_KCNTL_OUT : out std_logic; + SD_TX_CORRECT_DISP_OUT : out std_logic; + SD_RX_DATA_IN : in std_logic_vector(7 downto 0); + SD_RX_KCNTL_IN : in std_logic; + SD_RX_DISP_ERROR_IN : in std_logic; + SD_RX_CV_ERROR_IN : in std_logic; + SD_RX_SERDES_RST_OUT : out std_logic; + SD_RX_PCS_RST_OUT : out std_logic; + SD_TX_PCS_RST_OUT : out std_logic; + SD_RX_LOS_IN : in std_logic; + SD_SIGNAL_DETECTED_IN : in std_logic; + SD_RX_CDR_IN : in std_logic; + SD_TX_PLL_LOL_IN : in std_logic; + SD_QUAD_RST_OUT : out std_logic; TIMESTAMP_IN : in std_logic_vector(31 downto 0); DEST_ADDR_IN : in std_logic_vector(15 downto 0); GENERATE_PACKET_IN : in std_logic; - LED_GREEN : out std_logic; - LED_ORANGE : out std_logic; - LED_RED : out std_logic; - LED_YELLOW : out std_logic + SIZE_IN : in std_logic_vector(15 downto 0); + BUSY_OUT : out std_logic ); end component; component CNTester_random is - generic ( width : integer := 32 ); port ( CLK_IN : in std_logic; + RESET : in std_logic; GENERATE_IN : in std_logic; - RANDOM_OUT : out std_logic_vector (width-1 downto 0) --output vector + RANDOM_OUT : out std_logic_vector (31 downto 0) --output vector ); end component; @@ -243,6 +380,10 @@ port ( GSC_REPLY_READ_OUT : out std_logic; GSC_BUSY_IN : in std_logic; + CNT_GENERATE_PACKET_IN : in std_logic; + CNT_TIMESTAMP_IN : in std_logic_vector(31 downto 0); + CNT_DEST_ADDR_IN : in std_logic_vector(15 downto 0); + CNT_SIZE_IN : in std_logic_vector(15 downto 0); -- input for statistics from outside STAT_DATA_IN : in std_logic_vector(31 downto 0); STAT_ADDR_IN : in std_logic_vector(7 downto 0); @@ -334,6 +475,12 @@ port ( -- signals to/from hub MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); + CNT_GENERATE_PACKET_IN : in std_logic; + CNT_TIMESTAMP_IN : in std_logic_vector(31 downto 0); + CNT_DEST_ADDR_IN : in std_logic_vector(15 downto 0); + CNT_SIZE_IN : in std_logic_vector(15 downto 0); + CNT_BUSY_OUT : out std_logic; + GSC_CLK_IN : in std_logic; GSC_INIT_DATAREADY_OUT : out std_logic; GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); @@ -711,16 +858,6 @@ port( FT_RXD_OUT : out std_logic_vector(7 downto 0); FT_RX_EN_OUT : out std_logic; FT_RX_ER_OUT : out std_logic; - --SFP Connection - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_REFCLK_P_IN : in std_logic; - SD_REFCLK_N_IN : in std_logic; - SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic; -- SFP disable -- Autonegotiation stuff MR_RESET_IN : in std_logic; MR_MODE_IN : in std_logic; @@ -730,11 +867,23 @@ port( MR_AN_COMPLETE_OUT : out std_logic; MR_AN_ENABLE_IN : in std_logic; MR_RESTART_AN_IN : in std_logic; - -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) + + SD_RX_CLK_IN : in std_logic; + SD_TX_DATA_OUT : out std_logic_vector(7 downto 0); + SD_TX_KCNTL_OUT : out std_logic; + SD_TX_CORRECT_DISP_OUT : out std_logic; + SD_RX_DATA_IN : in std_logic_vector(7 downto 0); + SD_RX_KCNTL_IN : in std_logic; + SD_RX_DISP_ERROR_IN : in std_logic; + SD_RX_CV_ERROR_IN : in std_logic; + SD_RX_SERDES_RST_OUT : out std_logic; + SD_RX_PCS_RST_OUT : out std_logic; + SD_TX_PCS_RST_OUT : out std_logic; + SD_RX_LOS_IN : in std_logic; + SD_SIGNAL_DETECTED_IN : in std_logic; + SD_RX_CDR_IN : in std_logic; + SD_TX_PLL_LOL_IN : in std_logic; + SD_QUAD_RST_OUT : out std_logic ); end component; diff --git a/trb_net_gbe_protocols.vhd b/trb_net_gbe_protocols.vhd index cc5b6bb..9f1c59f 100644 --- a/trb_net_gbe_protocols.vhd +++ b/trb_net_gbe_protocols.vhd @@ -76,8 +76,8 @@ port ( TIMESTAMP_IN : in std_logic_vector(31 downto 0); DEST_ADDR_IN : in std_logic_vector(15 downto 0); + SIZE_IN : in std_logic_vector(15 downto 0); GENERATE_PACKET_IN : in std_logic; - -- debug DEBUG_OUT : out std_logic_vector(31 downto 0) );