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Computer Architecture and Programming Languages PhD @ University of Washington
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University of Washington
- Seattle, WA
- justg.us
- @gushfsmith
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uwsampl/lakeroad
uwsampl/lakeroad PublicFPGA synthesis tool powered by program synthesis
886 contributions in the last year
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Contribution activity
November 2023
Created 12 commits in 5 repositories
Created a pull request in uwsampl/lakeroad that received 2 comments
Antiunification/common subexpression enumeration experiments in Lakeroad egglog(/Churchroad)
+637
−3
lines changed
•
2
comments
Opened 2 other pull requests in 2 repositories
uwsampl/lakeroad-evaluation
1
merged
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Setup portfolio solving project
This contribution was made on Nov 10
uwsampl/lakeroad
1
merged
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Various user-facing improvements to portfolio solving script, to help with portfolio solving project
This contribution was made on Nov 9
Reviewed 3 pull requests in 1 repository
uwsampl/lakeroad
3 pull requests
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Add function to create replacement map based on input wire expressions.
This contribution was made on Nov 6
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Fix issue with
simulate_with_verilator.py
input parsingThis contribution was made on Nov 6 -
Add tests more test for typing rules that involve wires
This contribution was made on Nov 1
Created an issue in YosysHQ/oss-cad-suite-build that received 5 comments
Update Bitwuzla/seems like Bitwuzla is not origin/main version?
I'm confused on which version of Bitwuzla is in oss-cad-suite. From digging in the scripts, it seems like bitwuzla is pulled from origin/main. But …
5
comments
Opened 23 other issues in 3 repositories
uwsampl/lakeroad
14
open
1
closed
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Write extraction function that only extracts
apply
nodesThis contribution was made on Nov 26 -
Demonstrate an optimal mapping of permuter to ALMs (Intel challenge problem)
This contribution was made on Nov 26
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Do some kind of integration with Filament
This contribution was made on Nov 22
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Typing judgement tests
This contribution was made on Nov 22
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Generate module enumeration rewrites programmatically
This contribution was made on Nov 21
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Give types to AST/Module expressions in new IR
This contribution was made on Nov 21
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Create a "load Lakeroad" function that loads Lakeroad DSL into an
EGraph
This contribution was made on Nov 20 -
Convert Yosys Lakeroad backend to output to new egglog syntax
This contribution was made on Nov 15
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Merge CFGLUT5 PR
This contribution was made on Nov 10
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Return metadata about what solvers worked from lakeroad-portfolio.py
This contribution was made on Nov 9
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Current portfolio solver naively runs two copies of main.rkt; duplicates a lot of work
This contribution was made on Nov 9
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Deduplicate sub-expressions/sub-circuits in design (antiunification?)
This contribution was made on Nov 5
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Get rid of
value: unused
on output portsThis contribution was made on Nov 2 -
Does unequal input or output bitwidths on DSPs just do bitwidth promotion?
This contribution was made on Nov 1
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Simulate with Verilator script is producing the same inputs every time for 96 bit test in Vishal's PR
This contribution was made on Nov 1
uwsampl/lakeroad-evaluation
7
open
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Report bugs found in Diamond compilation
This contribution was made on Nov 6
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Quantify hardware savings
This contribution was made on Nov 6
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Add Multi-DSP designs to evaluation
This contribution was made on Nov 6
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Run Vivado tasks separate from other tasks, so that we can use more threads on other tasks
This contribution was made on Nov 1
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Decide on first end-to-end example
This contribution was made on Nov 1
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Explore
use_dsp = "simd"
This contribution was made on Nov 1 -
Generate resource reduction numbers
This contribution was made on Nov 1
kallepersson/DistractionFree
1
open
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Going into Distraction Free Mode exits fullscreen on Mac on Chrome
This contribution was made on Nov 5
18
contributions
in private repositories
Nov 1 – Nov 28