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* Add the framework for adding an arch specific module to the PCI bus…

…_manager.

* Implement such a module for x86 which currently exports only an MSI API.
* Implement the PCI part for configuring and enabling MSIs.
* Some automatic whitespace cleanup.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@36223 a95241bf-73f2-0310-859d-f6bbb57e9c96
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mmlr committed Apr 13, 2010
1 parent bafcab9 commit 2548ea219a5c97355b49de1523c8158887937220
@@ -83,7 +83,7 @@ typedef struct pci_info {
ulong rom_base_pci; /* rom base addr, viewed from pci */
uchar interrupt_line; /* interrupt line */
uchar interrupt_pin; /* interrupt pin */
ushort bridge_control;
ushort bridge_control;
ushort subsystem_id; /* subsystem (add-in card) id */
ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */
} h1;
@@ -109,7 +109,7 @@ typedef struct pci_info {
ushort secondary_status;
ushort bridge_control;
#endif /* __HAIKU_PCI_BUS_MANAGER_TESTING */
} h2;
} h2;
} u;
} pci_info;
@@ -221,7 +221,7 @@ struct pci_module_info {
#define PCI_primary_bus 0x18 /* (1 byte) */
#define PCI_secondary_bus 0x19 /* (1 byte) */
#define PCI_subordinate_bus 0x1A /* (1 byte) */
#define PCI_secondary_latency 0x1B /* (1 byte) latency of secondary bus */
#define PCI_secondary_latency 0x1B /* (1 byte) latency of secondary bus */
#define PCI_io_base 0x1C /* (1 byte) io base address register for 2ndry bus*/
#define PCI_io_limit 0x1D /* (1 byte) */
#define PCI_secondary_status 0x1E /* (2 bytes) */
@@ -236,7 +236,7 @@ struct pci_module_info {
#define PCI_sub_vendor_id_1 0x34 /* (2 bytes) */
#define PCI_sub_device_id_1 0x36 /* (2 bytes) */
#define PCI_bridge_rom_base 0x38
#define PCI_bridge_control 0x3E /* (2 bytes) */
#define PCI_bridge_control 0x3E /* (2 bytes) */
/* PCI type 2 header offsets */
@@ -245,7 +245,7 @@ struct pci_module_info {
#define PCI_primary_bus_2 0x18 /* (1 byte) */
#define PCI_secondary_bus_2 0x19 /* (1 byte) */
#define PCI_subordinate_bus_2 0x1A /* (1 byte) */
#define PCI_secondary_latency_2 0x1B /* (1 byte) latency of secondary bus */
#define PCI_secondary_latency_2 0x1B /* (1 byte) latency of secondary bus */
#define PCI_memory_base0_2 0x1C /* (4 bytes) */
#define PCI_memory_limit0_2 0x20 /* (4 bytes) */
#define PCI_memory_base1_2 0x24 /* (4 bytes) */
@@ -588,8 +588,8 @@ struct pci_module_info {
/** types of PCI header */
#define PCI_header_type_generic 0x00
#define PCI_header_type_PCI_to_PCI_bridge 0x01
#define PCI_header_type_generic 0x00
#define PCI_header_type_PCI_to_PCI_bridge 0x01
#define PCI_header_type_cardbus 0x02
@@ -677,6 +677,34 @@ struct pci_module_info {
#define PCI_pm_state_d2 0x02
#define PCI_pm_state_d3 0x03
/** MSI registers **/
#define PCI_msi_control 0x02
#define PCI_msi_address 0x04
#define PCI_msi_address_high 0x08
#define PCI_msi_data 0x08
#define PCI_msi_data_64bit 0x0c
#define PCI_msi_mask 0x10
#define PCI_msi_pending 0x14
/** MSI control register values **/
#define PCI_msi_control_enable 0x0001
#define PCI_msi_control_vector 0x0100
#define PCI_msi_control_64bit 0x0080
#define PCI_msi_control_mme_mask 0x0070
#define PCI_msi_control_mme_1 0x0000
#define PCI_msi_control_mme_2 0x0010
#define PCI_msi_control_mme_4 0x0020
#define PCI_msi_control_mme_8 0x0030
#define PCI_msi_control_mme_16 0x0040
#define PCI_msi_control_mme_32 0x0050
#define PCI_msi_control_mmc_mask 0x000e
#define PCI_msi_control_mmc_1 0x0000
#define PCI_msi_control_mmc_2 0x0002
#define PCI_msi_control_mmc_4 0x0004
#define PCI_msi_control_mmc_8 0x0006
#define PCI_msi_control_mmc_16 0x0008
#define PCI_msi_control_mmc_32 0x000a
#ifdef __cplusplus
}
#endif
@@ -0,0 +1,38 @@
#ifndef PCI_X86_H
#define PCI_X86_H
#include <SupportDefs.h>
#include <module.h>
typedef struct pci_x86_module_info {
module_info info;
uint8 (*get_msi_count)(
uint8 bus, /* bus number */
uint8 device, /* device # on bus */
uint8 function); /* function # in device */
status_t (*configure_msi)(
uint8 bus, /* bus number */
uint8 device, /* device # on bus */
uint8 function, /* function # in device */
uint8 count, /* count of vectors desired */
uint8 *startVector); /* first configured vector */
status_t (*unconfigure_msi)(
uint8 bus, /* bus number */
uint8 device, /* device # on bus */
uint8 function); /* function # in device */
status_t (*enable_msi)(
uint8 bus, /* bus number */
uint8 device, /* device # on bus */
uint8 function); /* function # in device */
status_t (*disable_msi)(
uint8 bus, /* bus number */
uint8 device, /* device # on bus */
uint8 function); /* function # in device */
} pci_x86_module_info;
#define B_PCI_X86_MODULE_NAME "bus_managers/pci/x86/v1"
#endif // PCI_X86_H
@@ -3,12 +3,13 @@ SubDir HAIKU_TOP src add-ons kernel bus_managers pci ;
UsePrivateKernelHeaders ;
UsePrivateHeaders shared ;
UsePrivateHeaders [ FDirName kernel util ] ;
UseHeaders [ FDirName $(SUBDIR) arch $(TARGET_ARCH) ] ;
KernelAddon pci :
pci.cpp
pci_fixup.cpp
pci_info.cpp
pci_module.c
pci_module.cpp
pci_root.cpp
pci_device.cpp
: pci_arch_bus_manager.a
@@ -2,12 +2,14 @@ SubDir HAIKU_TOP src add-ons kernel bus_managers pci arch x86 ;
SubDirHdrs [ FDirName $(SUBDIR) $(DOTDOT) $(DOTDOT) ] ;
UsePrivateHeaders kernel [ FDirName kernel arch x86 ] ;
UsePrivateHeaders kernel [ FDirName kernel arch x86 ] [ FDirName kernel util ] ;
KernelStaticLibrary pci_arch_bus_manager :
KernelStaticLibrary pci_arch_bus_manager :
pci_arch_info.cpp
pci_arch_module.cpp
pci_bios.c
pci_controller.c
pci_io.c
pci_irq.c
pci_msi.cpp
;
@@ -0,0 +1,7 @@
#include "pci_arch_info.h"
void
pci_read_arch_info(PCIDev *dev)
{
pci_read_msi_info(dev);
}
@@ -0,0 +1,13 @@
#ifndef _PCI_ARCH_INFO_H
#define _PCI_ARCH_INFO_H
#include "pci_msi.h"
typedef struct pci_arch_info {
msi_info msi;
} pci_arch_info;
void pci_read_arch_info(PCIDev *device);
#endif // _PCI_ARCH_INFO_H
@@ -0,0 +1,30 @@
#include <PCI_x86.h>
#include "pci_msi.h"
static int32
pci_arch_module_std_ops(int32 op, ...)
{
switch (op) {
case B_MODULE_INIT:
case B_MODULE_UNINIT:
return B_OK;
}
return B_BAD_VALUE;
}
pci_x86_module_info gPCIArchModule = {
{
B_PCI_X86_MODULE_NAME,
0,
pci_arch_module_std_ops
},
&pci_get_msi_count,
&pci_configure_msi,
&pci_unconfigure_msi,
&pci_enable_msi,
&pci_disable_msi
};
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