{"payload":{"header_redesign_enabled":false,"results":[{"id":"27832963","archived":false,"color":"#adb2cb","followers":1,"has_funding_file":false,"hl_name":"haneensa/CPU","hl_trunc_description":"simple CPU implementation on FPGA","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":27832963,"name":"CPU","owner_id":2872516,"owner_login":"haneensa","updated_at":"2017-11-28T11:03:37.664Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":53,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Ahaneensa%252FCPU%2B%2Blanguage%253AVHDL","metadata":null,"csrf_tokens":{"/haneensa/CPU/star":{"post":"aaIBT_YEufAGeBGo2feWO7_WmxvO6fEyd6gi4XhSU7-DgXGwwmn1WyOMcQSXPtPIBbqIiZ2ENMsk_iqXz_T5cQ"},"/haneensa/CPU/unstar":{"post":"1Qsneaeiw3HKfl3_CQShXzzVRA5O0XPdaYilpvi0D21VsBej3Iwx6zagGBLK76sePKxlG5wZ4CoBM-0OAmDz3Q"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"wnaS8YvtaeIMnWHBhnIVN-ilbs55WbFR3VEBqdLpA8M-dz9KJG2NFc7U5vAKyvGL9c0GdSBtxlyWcf1olJJPmA"}}},"title":"Repository search results"}