From 6b290b18721983f5a221aa13bedd58843a50eabb Mon Sep 17 00:00:00 2001 From: Dongjin Kim Date: Tue, 19 May 2015 16:00:32 +0900 Subject: [PATCH] PD #96169: hdmitx: update hpll setting Squashed commit of the following: commit 0fa46efbdb1eae9771c3d5cf9b1f558ac725301f Author: zongdong.jiao Date: Fri Oct 10 21:37:53 2014 +0800 PD #96169: hdmitx: update hpll setting commit 795cefa28525f39e6ba5a8f113caf4f01f6466ba Author: zongdong.jiao Date: Fri Oct 10 21:37:10 2014 +0800 PD #96169: hdmitx: merge 97042 commit to a single commit Conflicts: drivers/amlogic/display/vout/enc_clk_config.c Change-Id: Ib5ad1cc6bd390eeba093eb6b34fc256de470b595 Signed-off-by: Dongjin Kim --- arch/arm/mach-meson8/hdmi_tx_hw/hdmi_tx_hw.c | 1 + arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_hw.c | 107 ++++++-- .../mach-meson8b/include/mach/hdmi_tx_reg.h | 3 + drivers/amlogic/display/vout/enc_clk_config.c | 247 +++++------------- include/linux/amlogic/vout/enc_clk_config.h | 1 + 5 files changed, 167 insertions(+), 192 deletions(-) diff --git a/arch/arm/mach-meson8/hdmi_tx_hw/hdmi_tx_hw.c b/arch/arm/mach-meson8/hdmi_tx_hw/hdmi_tx_hw.c index 2e8efc031da4ab..f8c44aad671e4c 100644 --- a/arch/arm/mach-meson8/hdmi_tx_hw/hdmi_tx_hw.c +++ b/arch/arm/mach-meson8/hdmi_tx_hw/hdmi_tx_hw.c @@ -2861,6 +2861,7 @@ static void cts_test(hdmitx_dev_t* hdmitx_device) printk("dis: %d [%d] %d [%d] %d\n", cts_buf[i].val - cts_buf[i-1].val, i, cts_buf[i].val, i - 1, cts_buf[i - 1].val); } + min = max = cts_buf[0].val; for(i = 0; i < AUD_CTS_LOG_NUM; i++) { total += cts_buf[i].val; if(min > cts_buf[i].val) diff --git a/arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_hw.c b/arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_hw.c index e21b17f44394f9..3fdf36dbeb7996 100755 --- a/arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_hw.c +++ b/arch/arm/mach-meson8b/hdmi_tx_hw/hdmi_tx_hw.c @@ -1474,21 +1474,29 @@ void hdmi_hw_init(hdmitx_dev_t* hdmitx_device) delay_us(10); } -#ifdef CONFIG_ARCH_MESON6 -// TODO, need test in m8 -// When 1080p50hz output, we shall manually configure +// When have below format output, we shall manually configure // bolow register to get stable Video Timing. -static void hdmi_reconfig_packet_setting(void) +static void hdmi_reconfig_packet_setting(HDMI_Video_Codes_t vic) { - hdmi_wr_reg(TX_PACKET_ALLOC_ACTIVE_1, 0x01); - hdmi_wr_reg(TX_PACKET_ALLOC_ACTIVE_2, 0x12); - hdmi_wr_reg(TX_PACKET_ALLOC_EOF_1, 0x10); - hdmi_wr_reg(TX_PACKET_ALLOC_EOF_2, 0x12); - hdmi_wr_reg(TX_PACKET_ALLOC_SOF_1, 0xb6); - hdmi_wr_reg(TX_PACKET_ALLOC_SOF_2, 0x11); - hdmi_wr_reg(TX_PACKET_CONTROL_1, (hdmi_rd_reg(TX_PACKET_CONTROL_1)) | (1 << 7)); // bit[7]: forced_packet_timing + switch(vic) { + case HDMI_1080p50: + hdmi_wr_reg(TX_PACKET_CONTROL_1, 0x3a); //0x7e + hdmi_wr_reg(TX_PACKET_ALLOC_ACTIVE_1, 0x01); //0x78 + hdmi_wr_reg(TX_PACKET_ALLOC_ACTIVE_2, 0x12); //0x79 + hdmi_wr_reg(TX_PACKET_ALLOC_EOF_1, 0x10); //0x7a + hdmi_wr_reg(TX_PACKET_ALLOC_EOF_2, 0x12); //0x7b + hdmi_wr_reg(TX_CORE_ALLOC_VSYNC_0, 0x01); //0x81 + hdmi_wr_reg(TX_CORE_ALLOC_VSYNC_1, 0x00); //0x82 + hdmi_wr_reg(TX_CORE_ALLOC_VSYNC_2, 0x0a); //0x83 + hdmi_wr_reg(TX_PACKET_ALLOC_SOF_1, 0xb6); //0x7c + hdmi_wr_reg(TX_PACKET_ALLOC_SOF_2, 0x11); //0x7d + hdmi_wr_reg(TX_PACKET_CONTROL_1, 0xba); //0x7e + break; + default: + break; + } + printk("reconfig packet setting done\n"); } -#endif static void hdmi_hw_reset(hdmitx_dev_t* hdmitx_device, Hdmi_tx_video_para_t *param) { @@ -1842,11 +1850,7 @@ static void hdmi_hw_reset(hdmitx_dev_t* hdmitx_device, Hdmi_tx_video_para_t *par hdmi_wr_reg(TX_SYS5_TX_SOFT_RESET_2, 0x00); } } -#ifdef CONFIG_ARCH_MESON6 //todo - if(param->VIC == HDMI_1080p50) { - hdmi_reconfig_packet_setting(); // For 1080p50hz only - } -#endif + hdmi_reconfig_packet_setting(param->VIC); } static void hdmi_audio_init(unsigned char spdif_flag) @@ -3012,6 +3016,71 @@ static void hdmitx_print_info(hdmitx_dev_t* hdmitx_device, int printk_flag) hdmi_print(INF, "------------------\n"); } +typedef struct { + unsigned int val : 20; + unsigned int stable: 1; +}aud_cts_log_t; + +static inline unsigned int get_msr_cts(void) +{ + unsigned int ret; + + ret = hdmi_rd_reg(TX_TMDS_ST_CLOCK_METER_1); + ret += (hdmi_rd_reg(TX_TMDS_ST_CLOCK_METER_2) << 8); + ret += ((hdmi_rd_reg(TX_TMDS_ST_CLOCK_METER_3) & 0xf) << 16); + + return ret; +} + +static inline unsigned int get_msr_cts_st(void) +{ + return !!(hdmi_rd_reg(TX_TMDS_ST_CLOCK_METER_3) & 0x80); +} + +#define AUD_CTS_LOG_NUM 1000 +aud_cts_log_t cts_buf[AUD_CTS_LOG_NUM]; +static void cts_test(hdmitx_dev_t* hdmitx_device) +{ + int i, j; + unsigned int min = 0, max = 0, total = 0; + + printk("\nhdmitx: audio: cts test\n"); + memset(cts_buf, 0, sizeof(cts_buf)); + for(i = 0; i < AUD_CTS_LOG_NUM; i++) { + cts_buf[i].val = get_msr_cts(); + cts_buf[i].stable = get_msr_cts_st(); + mdelay(1); + } + + printk("cts unstable:\n"); + for(i = 0, j = 0; i < AUD_CTS_LOG_NUM; i++) { + if(cts_buf[i].stable == 0) { + printk("%d ", i); + j ++; + if(((j+1) & 0xf) == 0) + printk("\n"); + } + } + + printk("\ncts change:\n"); + for(i = 1; i < AUD_CTS_LOG_NUM; i++) { + if(cts_buf[i].val > cts_buf[i-1].val) + printk("dis: +%d [%d] %d [%d] %d\n", cts_buf[i].val - cts_buf[i-1].val, i, cts_buf[i].val, i - 1, cts_buf[i - 1].val); + if(cts_buf[i].val < cts_buf[i-1].val) + printk("dis: %d [%d] %d [%d] %d\n", cts_buf[i].val - cts_buf[i-1].val, i, cts_buf[i].val, i - 1, cts_buf[i - 1].val); + } + + min = max = cts_buf[0].val; + for(i = 0; i < AUD_CTS_LOG_NUM; i++) { + total += cts_buf[i].val; + if(min > cts_buf[i].val) + min = cts_buf[i].val; + if(max < cts_buf[i].val) + max = cts_buf[i].val; + } + printk("\nCTS Min: %d Max: %d Avg: %d/1000\n\n", min, max, total); +} + static void hdmitx_debug(hdmitx_dev_t* hdmitx_device, const char* buf) { char tmpbuf[128]; @@ -3027,6 +3096,10 @@ static void hdmitx_debug(hdmitx_dev_t* hdmitx_device, const char* buf) hdmitx_dump_tvenc_reg(hdmitx_device->cur_VIC, 1); return; } + else if(strncmp(tmpbuf, "ctstest", 7) == 0) { + cts_test(hdmitx_device); + return; + } else if(strncmp(tmpbuf, "ss", 2) == 0) { printk("hdmitx_device->output_blank_flag: 0x%x\n", hdmitx_device->output_blank_flag); printk("hdmitx_device->hpd_state: 0x%x\n", hdmitx_device->hpd_state); diff --git a/arch/arm/mach-meson8b/include/mach/hdmi_tx_reg.h b/arch/arm/mach-meson8b/include/mach/hdmi_tx_reg.h index 96f6919272a4da..46888c8b7a1bdd 100644 --- a/arch/arm/mach-meson8b/include/mach/hdmi_tx_reg.h +++ b/arch/arm/mach-meson8b/include/mach/hdmi_tx_reg.h @@ -222,6 +222,9 @@ typedef struct { #define TX_CORE_CALIB_VALUE TX_BASE_ADDR+0x0F7 #define TX_CORE_EDID_CONFIG_MORE TX_BASE_ADDR+0x080 +#define TX_CORE_ALLOC_VSYNC_0 TX_BASE_ADDR+0x081 +#define TX_CORE_ALLOC_VSYNC_1 TX_BASE_ADDR+0x082 +#define TX_CORE_ALLOC_VSYNC_2 TX_BASE_ADDR+0x083 // HDCP shadow register #define TX_HDCP_SHW_BKSV_0 TX_BASE_ADDR+0x100 diff --git a/drivers/amlogic/display/vout/enc_clk_config.c b/drivers/amlogic/display/vout/enc_clk_config.c index 513c6c2a0e3e7e..156e1e09624263 100644 --- a/drivers/amlogic/display/vout/enc_clk_config.c +++ b/drivers/amlogic/display/vout/enc_clk_config.c @@ -55,91 +55,41 @@ static void set_hpll_clk_out(unsigned clk) printk("config HPLL\n"); #if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8 - if(IS_MESON_M8M2_CPU){ - aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c88000); - aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca563823); - aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x40238100); - aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012286); - aml_write_reg32(P_HHI_VID2_PLL_CNTL2, 0x430a800); // internal LDO share with HPLL & VIID PLL - switch(clk){ - case 2970: - aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c84e00); - aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xce49c822); - aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4123b100); - aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385); - - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d); - printk("waiting HPLL lock\n"); - while(!(aml_read_reg32(P_HHI_VID_PLL_CNTL) & (1 << 31))) { - ; - } - h_delay(); - aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385); // optimise HPLL VCO 2.97GHz performance - break; - case 2160: - aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000); - aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823); - aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100); - aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042d); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042d); - while(!(aml_read_reg32(P_HHI_VID_PLL_CNTL) & (1 << 31))) { - ; - } - break; - case 1488: - aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8ce00); - aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100); - aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023); - aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d); - while(!(aml_read_reg32(P_HHI_VID_PLL_CNTL) & (1 << 31))) { - ; - } - break; - case 1080: - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000042d); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042d); - break; - case 1066: - WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x42a); - break; - case 1058: - WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x422); - break; - case 1086: - WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e); - break; - case 1296: - aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c88000); - aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca49b022); - aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0023b100); - aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x600c0436); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x400c0436); - aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385); - break; - default: - printk("error hpll clk: %d\n", clk); - break; - } - if(clk < 2970) - aml_write_reg32(P_HHI_VID_PLL_CNTL5, (aml_read_reg32(P_HHI_VID_PLL_CNTL5) & (~(0xf << 12))) | (0x6 << 12)); - } -#endif - -#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8B + printk("%s[%d] clk = %d\n", __func__, __LINE__, clk); aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c88000); aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca563823); aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x40238100); aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012286); aml_write_reg32(P_HHI_VID2_PLL_CNTL2, 0x430a800); // internal LDO share with HPLL & VIID PLL switch(clk){ + case 2971: // only for 4k mode + aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000); + aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xce49c022); + aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4123b100); + aml_set_reg32_bits(P_HHI_VID2_PLL_CNTL2, 1, 16, 1); + aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385); + aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d); + aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d); + WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); + h_delay(); + aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385); // optimise HPLL VCO 2.97GHz performance + aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00); + break; + case 2970: // for 1080p/i 720p mode + aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000); + aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023); + aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4123b100); + aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385); + aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d); + aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d); + WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); + h_delay(); + aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385); // optimise HPLL VCO 2.97GHz performance + aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00); + break; case 2160: - aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c80000); - aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x0a563823); + aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000); + aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023); aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100); aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385); aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042d); @@ -235,15 +185,6 @@ static void set_hpll_clk_out(unsigned clk) aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x40010429); WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); break; - case 1488: - aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8ce00); - aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100); - aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023); - aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d); - WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); - break; case 1422: aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000); aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100); @@ -272,21 +213,6 @@ static void set_hpll_clk_out(unsigned clk) aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042d); WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); break; - case 1066: - aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8c000); - aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4023d100); - aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a7ad023); - aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12286); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000042a); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042a); - WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); - break; - case 1058: - WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x422); - break; - case 1086: - WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e); - break; case 1296: aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c88000); aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca49b022); @@ -304,7 +230,8 @@ static void set_hpll_clk_out(unsigned clk) aml_write_reg32(P_HHI_VID_PLL_CNTL5, (aml_read_reg32(P_HHI_VID_PLL_CNTL5) & (~(0xf << 12))) | (0x6 << 12)); #endif -#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8 +#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8B + printk("%s[%d] clk = %d\n", __func__, __LINE__, clk); aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c88000); aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xca563823); aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x40238100); @@ -312,46 +239,26 @@ static void set_hpll_clk_out(unsigned clk) aml_write_reg32(P_HHI_VID2_PLL_CNTL2, 0x430a800); // internal LDO share with HPLL & VIID PLL switch(clk){ case 2970: - aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c84e00); - aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0xce49c822); + aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000); + aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023); aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x4123b100); aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00012385); aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d); aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d); - printk("waiting HPLL lock\n"); - while(!(aml_read_reg32(P_HHI_VID_PLL_CNTL) & (1 << 31))) { - ; - } + WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); h_delay(); aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x00016385); // optimise HPLL VCO 2.97GHz performance - break; - case 1488: - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000043d); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000043d); - printk("waiting HPLL lock[%d]\n", __LINE__); - while(!(aml_read_reg32(P_HHI_VID_PLL_CNTL) & (1 << 31))) { - ; - } - aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c8ce00); - break; - case 1080: - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000042d); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042d); + aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84e00); break; case 2160: - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000045a); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000045a); - break; - case 1066: - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6000042a); - aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4000042a); - break; - case 1058: - WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x422); - break; - case 1086: - WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e); + aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x69c84000); + aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a46c023); + aml_write_reg32(P_HHI_VID_PLL_CNTL4, 0x0123b100); + aml_write_reg32(P_HHI_VID_PLL_CNTL5, 0x12385); + aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x6001042d); + aml_write_reg32(P_HHI_VID_PLL_CNTL, 0x4001042d); + WAIT_FOR_PLL_LOCKED(P_HHI_VID_PLL_CNTL); break; case 1296: aml_write_reg32(P_HHI_VID_PLL_CNTL2, 0x59c88000); @@ -371,6 +278,7 @@ static void set_hpll_clk_out(unsigned clk) #endif #if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6 + printk("%s[%d] clk = %d\n", __func__, __LINE__, clk); switch(clk){ case 1488: WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x43e); @@ -393,11 +301,6 @@ static void set_hpll_clk_out(unsigned clk) printk("error hpll clk: %d\n", clk); break; } -#endif -#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 - // Improve HDMI HPLL Long TIE - if( clk != 1296 ) // 1296MHz is only for 480cvbs/576cvbs on m8 serials, and is not suitable with 0x8a56d023 - aml_write_reg32(P_HHI_VID_PLL_CNTL3, 0x8a56d023); #endif printk("config HPLL done\n"); } @@ -411,11 +314,8 @@ static void set_hpll_hdmi_od(unsigned div) case 2: WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 1, 18, 2); break; - case 3: - WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 1, 16, 2); - break; case 4: - WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 3, 18, 2); + WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 2, 18, 2); break; case 8: WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 1, 16, 2); @@ -588,8 +488,6 @@ static void set_vdac1_div(unsigned div) // hdmi_tx_pixel_div unsigned encp_div unsigned enci_div unsigned enct_div unsigned ecnl_div; static enc_clk_val_t setting_enc_clk_val_m8m2[] = { - -#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8 {VMODE_480I, 2160, 8, 1, 1, VIU_ENCI, 5, 4, 2,-1, 2, -1, -1, 2, -1}, {VMODE_480I_RPT, 2160, 4, 1, 1, VIU_ENCI, 5, 4, 2,-1, 4, -1, -1, 2, -1}, {VMODE_480CVBS, 1296, 4, 1, 1, VIU_ENCI, 6, 4, 2,-1, 2, -1, -1, 2, -1}, @@ -600,21 +498,20 @@ static enc_clk_val_t setting_enc_clk_val_m8m2[] = { {VMODE_576CVBS, 1296, 4, 1, 1, VIU_ENCI, 6, 4, 2,-1, 2, -1, -1, 2, -1}, {VMODE_576P, 2160, 8, 1, 1, VIU_ENCP, 5, 4, 2, 1, -1, -1, -1, 1, -1}, {VMODE_576P_RPT, 2160, 2, 1, 1, VIU_ENCP, 5, 4, 1, 2, -1, -1, -1, 1, -1}, - {VMODE_720P, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, - {VMODE_1080I, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, - {VMODE_1080P, 1488, 1, 1, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_720P_50HZ, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, - {VMODE_1080I_50HZ, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, - {VMODE_1080P_50HZ, 1488, 1, 1, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_1080P_24HZ, 1488, 2, 1, 1, VIU_ENCP, 10, 2, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_4K2K_30HZ, 2970, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_4K2K_25HZ, 2970, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_4K2K_24HZ, 2970, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_4K2K_SMPTE, 2970, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_720P, 2970, 4, 2, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, + {VMODE_1080I, 2970, 4, 2, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, + {VMODE_1080P, 2970, 2, 2, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_720P_50HZ, 2970, 4, 2, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, + {VMODE_1080I_50HZ, 2970, 4, 2, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, + {VMODE_1080P_50HZ, 2970, 2, 2, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_1080P_24HZ, 2970, 4, 2, 1, VIU_ENCP, 10, 2, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_4K2K_30HZ, 2971, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_4K2K_25HZ, 2971, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_4K2K_24HZ, 2971, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_4K2K_SMPTE, 2971, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, {VMODE_VGA, 1066, 3, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, 1}, {VMODE_SVGA, 1058, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, 1}, {VMODE_XGA, 1085, 1, 1, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, 1}, -#endif }; static enc_clk_val_t setting_enc_clk_val[] = { @@ -625,7 +522,7 @@ static enc_clk_val_t setting_enc_clk_val[] = { {VMODE_576I, 2160, 8, 1, 1, VIU_ENCI, 5, 4, 2,-1, 2, -1, -1, 2, -1}, {VMODE_576CVBS, 1296, 4, 1, 1, VIU_ENCI, 6, 4, 2,-1, 2, -1, -1, 2, -1}, {VMODE_576P, 2160, 8, 1, 1, VIU_ENCP, 5, 4, 2, 1, -1, -1, -1, 1, -1}, - {VMODE_720P, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, + {VMODE_720P, 2970, 4, 2, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, {VMODE_800P, 1422, 2, 2, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, // MDRJR Verify {VMODE_800X480P_60HZ, 2380, 8, 4, 1, VIU_ENCP, 10, 4, 1, 1, -1, -1, -1, 1, -1}, {VMODE_1366X768P_60HZ, 1716, 2, 2, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, @@ -636,12 +533,12 @@ static enc_clk_val_t setting_enc_clk_val[] = { {VMODE_1360X768P_60HZ, 1710, 2, 2, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, {VMODE_1440X900P_60HZ, 2130, 2, 2, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, {VMODE_1680X1050P_60HZ, 2925, 2, 2, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_1080I, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, - {VMODE_1080P, 1488, 1, 1, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_720P_50HZ, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, - {VMODE_1080I_50HZ, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, - {VMODE_1080P_50HZ, 1488, 1, 1, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_1080P_24HZ, 1488, 2, 1, 1, VIU_ENCP, 10, 2, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_1080I, 2970, 4, 2, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, + {VMODE_1080P, 2970, 2, 2, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_720P_50HZ, 2970, 4, 2, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, + {VMODE_1080I_50HZ, 2970, 4, 2, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, + {VMODE_1080P_50HZ, 2970, 2, 2, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_1080P_24HZ, 2970, 4, 2, 1, VIU_ENCP, 10, 2, 1, 1, -1, -1, -1, 1, -1}, {VMODE_VGA, 2014, 8, 1, 1, VIU_ENCP, 10, 4, 1, 1, -1, -1, -1, 1, -1}, {VMODE_SVGA, 1058, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, 1}, {VMODE_XGA, 1085, 1, 1, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, 1}, @@ -660,17 +557,17 @@ static enc_clk_val_t setting_enc_clk_val[] = { {VMODE_576CVBS, 1296, 4, 1, 1, VIU_ENCI, 6, 4, 2,-1, 2, -1, -1, 2, -1}, {VMODE_576P, 1080, 4, 1, 1, VIU_ENCP, 5, 4, 2, 1, -1, -1, -1, 1, -1}, {VMODE_576P_RPT, 2160, 2, 1, 1, VIU_ENCP, 5, 4, 1, 2, -1, -1, -1, 1, -1}, - {VMODE_720P, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, - {VMODE_1080I, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, - {VMODE_1080P, 1488, 1, 1, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_720P_50HZ, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, - {VMODE_1080I_50HZ, 1488, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, - {VMODE_1080P_50HZ, 1488, 1, 1, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_1080P_24HZ, 1488, 2, 1, 1, VIU_ENCP, 10, 2, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_4K2K_30HZ, 2970, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_4K2K_25HZ, 2970, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_4K2K_24HZ, 2970, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, - {VMODE_4K2K_SMPTE, 2970, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_720P, 2970, 4, 2, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, + {VMODE_1080I, 2970, 4, 2, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, + {VMODE_1080P, 2970, 2, 2, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_720P_50HZ, 2970, 4, 2, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, + {VMODE_1080I_50HZ, 2970, 4, 2, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, -1}, + {VMODE_1080P_50HZ, 2970, 2, 2, 1, VIU_ENCP, 10, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_1080P_24HZ, 2970, 4, 2, 1, VIU_ENCP, 10, 2, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_4K2K_30HZ, 2971, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_4K2K_25HZ, 2971, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_4K2K_24HZ, 2971, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, + {VMODE_4K2K_SMPTE, 2971, 1, 2, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, -1}, {VMODE_VGA, 1066, 3, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, 1}, {VMODE_SVGA, 1058, 2, 1, 1, VIU_ENCP, 10, 1, 2, 1, -1, -1, -1, 1, 1}, {VMODE_XGA, 1085, 1, 1, 1, VIU_ENCP, 5, 1, 1, 1, -1, -1, -1, 1, 1}, diff --git a/include/linux/amlogic/vout/enc_clk_config.h b/include/linux/amlogic/vout/enc_clk_config.h index dac36100906219..fa32194c2009ea 100644 --- a/include/linux/amlogic/vout/enc_clk_config.h +++ b/include/linux/amlogic/vout/enc_clk_config.h @@ -32,6 +32,7 @@ typedef struct enc_clk_val{ unsigned encl_div; unsigned vdac0_div; unsigned vdac1_div; + unsigned unused; // prevent compile error\r }enc_clk_val_t;