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drm: exynos: Add a pixel clock to support Vu5A
To support Vu5A, a pixel clock, 33.9MHz is needed. But, there is no exact hdmi phy table of exynos5422, so the cloest table will be used as a workaround. - Vu5A timing Detailed mode: Clock 33.900 MHz, 476 mm x 268 mm 800 844 932 1056 hborder 0 480 483 489 535 vborder 0 +hsync +vsync Change-Id: Ia361526ecbcf83c714ccef62f878f5f665a4caa0
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