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ODROID-XU3/XU4: add command 'dmc' to set lpddr3 frequency on u-boot s…

…tage

Change-Id: I350bd655b75ccdd86fed58bdb9efc1e03996e651
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Joy Cho
Joy Cho committed May 22, 2017
1 parent 5535cc9 commit 677e9e1bf1ae604100dd389c11f937dd17605776
Showing with 118 additions and 0 deletions.
  1. +1 −0 common/Makefile
  2. +115 −0 common/cmd_dmc.c
  3. +2 −0 include/configs/odroid.h
@@ -175,6 +175,7 @@ COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o
COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
COBJS-$(CONFIG_CMD_SPL) += cmd_spl.o
COBJS-$(CONFIG_CMD_ZFS) += cmd_zfs.o
COBJS-$(CONFIG_CMD_DMC) += cmd_dmc.o

# others
ifdef CONFIG_DDR_SPD
@@ -0,0 +1,115 @@
/*
* Set LPDDR3 frequency and DMC for Exynos5422
*
* Copyright (C) 2017 Joy Cho <joy.cho@hardkernel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>

#define DREXI_0 0x10C20000
#define DREXI_1 0x10C30000

int set_cmu(int freq)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)EXYNOS5_CLOCK_BASE;

/* set BPLL_LOCK, BPLL_CON1 and BPLL_CON0 */
switch (freq) {
case 933:
writel(0x00000320, &clk->bpll_lock);
writel(0x0020F300, &clk->bpll_con1);
writel(0x81370401, &clk->bpll_con0);
break;
case 825:
writel(0x00000320, &clk->bpll_lock);
writel(0x0020F300, &clk->bpll_con1);
writel(0x81130401, &clk->bpll_con0);
break;
case 728:
writel(0x00000258, &clk->bpll_lock);
writel(0x0020F300, &clk->bpll_con1);
writel(0x80B60301, &clk->bpll_con0);
break;
case 633:
writel(0x00000320, &clk->bpll_lock);
writel(0x0020F300, &clk->bpll_con1);
writel(0x80D30401, &clk->bpll_con0);
break;
default:
printf("no available frequency - %dMHz\n", freq);
return 0;
}

/* check the 29th bit (LOCKED) to confirm PLL locking */
while(!(readl(&clk->bpll_con0) & (0x1 << 29)));

return 1;
}

void set_dmc(int freq, u32 drex_addr)
{
/* set TIMINGROW0, TIMINGDATA0 and TIMINGPOWER0 */
switch (freq) {
case 933:
writel(0x3D6BA816, drex_addr+0x0034);
writel(0x4742086E, drex_addr+0x0038);
writel(0x60670447, drex_addr+0x003C);
break;
case 825:
writel(0x365A9713, drex_addr+0x0034);
writel(0x4740085E, drex_addr+0x0038);
writel(0x543A0446, drex_addr+0x003C);
break;
case 728:
writel(0x30598651, drex_addr+0x0034);
writel(0x3730085E, drex_addr+0x0038);
writel(0x4C330336, drex_addr+0x003C);
break;
case 633:
writel(0x2A48758F, drex_addr+0x0034);
writel(0x3730085E, drex_addr+0x0038);
writel(0x402D0335, drex_addr+0x003C);
break;
default:
printf("no available frequency - %dMHz\n", freq);
break;
}
}

int do_dmc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int freq;

if (argc != 2)
return cmd_usage(cmdtp);
else
freq = simple_strtoul(argv[1], NULL, 10);

if (!set_cmu(freq))
return cmd_usage(cmdtp);

set_dmc(freq, DREXI_0);
set_dmc(freq, DREXI_1);

return 1;
}

U_BOOT_CMD(
dmc, 2, 0, do_dmc,
"Set LPDDR3 clock",
"dmc <lpddr3 frequency>\n"
"ex) dmc 933\n"
"lpddr3 frequency list - 933/825/728/633\n");
@@ -491,4 +491,6 @@
#define WRESET (1 << 10)
#define SYS_WDTRESET (1 << 9)

/* DMC */
#define CONFIG_CMD_DMC
#endif /* __CONFIG_H */

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