From d31aac453eaa0b56a998c3cca5d2efd4c55209af Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Mon, 13 Mar 2023 15:22:00 -0700 Subject: [PATCH] Flush the dcd data on reset --- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 32c2fc0293..91d5524b6b 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -48,6 +48,8 @@ #define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) +// Clean means to push any cached changes to RAM and invalidate "removes" the +// entry from the cache. #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1 #define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr #else @@ -199,6 +201,8 @@ static void bus_reset(uint8_t rhport) _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID; _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only + + CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); } void dcd_init(uint8_t rhport)