diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl
index 09bd0769..8c8fa6f6 100644
--- a/synthesis/build_defs.bzl
+++ b/synthesis/build_defs.bzl
@@ -160,6 +160,7 @@ def _synthesize_design_impl(ctx):
         "LIBERTY": default_liberty_file,
         "OUTPUT": output_file,
         "STANDARD_CELL_BLACK_BOX": standard_cell_black_box,
+        "SYNTH_ADDITIONAL_ARGS": ctx.attr.synth_additional_args,
         "TOP": ctx.attr.top_module,
         "UHDM_FLIST": uhdm_flist,
     }
@@ -385,6 +386,11 @@ synthesize_rtl = rule(
             providers = [StandardCellInfo],
             default = "@com_google_skywater_pdk_sky130_fd_sc_hd//:sky130_fd_sc_hd",
         ),
+        "synth_additional_args": attr.string(
+            mandatory = False,
+            doc = "Additional args for the Yosys synth pass",
+            default = "",
+        ),
         "synth_tcl": attr.label(
             default = Label("//synthesis:synth.tcl"),
             allow_single_file = True,
diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl
index c4c1cdff..f1cf3d73 100644
--- a/synthesis/synth.tcl
+++ b/synthesis/synth.tcl
@@ -10,6 +10,7 @@
 # OUTPUT = verilog file for synthesis output
 # STATS_JSON = json file for structured stats output
 # EARLY_TECHMAP = verilog/system verilog file for early techmap process
+# SYNTH_ADDITIONAL_ARGS = Additional args for the Yosys synth pass
 
 yosys -import
 
@@ -79,7 +80,12 @@ yosys delete {*/t:$print}
 # pass.
 yosys opt_clean -purge
 
-yosys synth -top $top -noshare
+set synth_args "-noshare"
+if { [info exists ::env(SYNTH_ADDITIONAL_ARGS)] && ![string equal $::env(SYNTH_ADDITIONAL_ARGS) ""] } {
+  set synth_args "$synth_args $::env(SYNTH_ADDITIONAL_ARGS)"
+}
+
+yosys synth -top $top {*}$synth_args
 
 # Remove internal only aliases for public nets and then give created instances
 # useful names. At this stage it is all the other synthesizable constructs.