Register Documentation

Yukimasa Sugizaki edited this page May 1, 2015 · 5 revisions

Register Documentation

This document was automatically generated on 2013-02-06 13:40 from the videocore register database, git commit c4f8bc6ce1f96314887ea1686e2c6f4f79ec59bb. Do not modify!

List of MMIO Regions

Address Size Name Description
0x7e000000 0x1000 MULT Multicore Sync Block
0x7e001000 0x1000 CCPT Compact Camera Port 2 TX
0x7e002000 0x1000 INTE VC Interrupt Controller
0x7e003000 0x1000 TIMER System Timers
0x7e004000 0x1000 TXP
0x7e005000 0x1000 JPEG
0x7e006000 0x1000 MPHI Message-based Parallel Host Interface
0x7e007000 0x1000 DMA DMA0-14
0x7e009000 0x1000 ARBA
0x7e00a000 0x1000 BRDG
0x7e00b000 0x1000 ARMCB ARM Control Block
0x7e100000 0x1000 PM Power Management
0x7e101000 0x1000 CM Clock Management
0x7e102000 0x1000 A2W
0x7e103000 0x1000 AVS Audio Video Standard
0x7e104000 0x1000 RNG Random Number Generator
0x7e200000 0x1000 GPIO General Purpose IO
0x7e201000 0x1000 UART0 UART0
0x7e202000 0x1000 ALTMMC Alternate MMC
0x7e203000 0x1000 PCM
0x7e204000 0x1000 SPI0
0x7e205000 0x1000 BSC0
0x7e206000 0x2000 PIXV Pixelvalue
0x7e208000 0x1000 DPI
0x7e209000 0x1000 DSI Display Serial Interface
0x7e20c000 0x1000 PWM0 Pulse Width Modulator
0x7e20d000 0x1000 PERM
0x7e20e000 0x1000 TEC
0x7e20f000 0x1000 OTP0 One Time Programmable Memory
0x7e210000 0x1000 SLIM SLIMbus
0x7e211000 0x1000 CPG
0x7e212000 0x1000 UNK212000
0x7e213000 0x1000 AVSP
0x7e214000 0x1000 UNK214000
0x7e215000 0x1000 AUX Auxiliaries
0x7e300000 0x1000 EMMC EMMC
0x7e400000 0x1000 DDRV
0x7e600000 0x1000 SMI
0x7e804000 0x1000 BSC1 BSC1
0x7e805000 0x1000 BSC2 BSC2
0x7e980000 0x1000 USB USB
0x7ec00000 0x1000 V3D V3D
0x7ee00000 0x1000 SDCO SDRAM Controller
0x7ee01000 0x1000 L2CC Level 2 Cache Controller
0x7ee02000 0x1000 L1CC Level 1 Cache Controller
0x7ee04000 0x1000 ARBR
0x7ee05000 0x1000 DMA15
0x7ee06000 0x1000 UNKe06000
0x7ee07000 0x1000 DCRC
0x7ee08000 0x1000 AXIP

MULT: Multicore Sync Block

Description

Found in "platform.h". This region is abused as "Fake framebuffer device".

Registers

Address Access Name Description

INTE: VC Interrupt Controller

Description

TBD

Registers

Address Access Name Description
0x7e002000 ? INTE_UNK_0x0
0x7e002004 ? INTE_UNK_0x4
0x7e002008 ? INTE_UNK_0x8
0x7e00200c ? INTE_UNK_0xc
0x7e002010 ? INTE_UNK_0x10
0x7e002014 ? INTE_UNK_0x14
0x7e002018 ? INTE_UNK_0x18
0x7e00201c ? INTE_UNK_0x1c
0x7e002020 ? INTE_UNK_0x20
0x7e002024 ? INTE_UNK_0x24
0x7e002028 ? INTE_UNK_0x28
0x7e00202c ? INTE_UNK_0x2c
0x7e002030 ? INTE_TABLE_PTR Interrupt table address
0x7e002034 ? INTE_UNK_0x34
0x7e002038 ? INTE_UNK_0x38
0x7e002040 ? INTE_UNK_0x40
0x7e002044 ? INTE_UNK_0x44

Unknown Registers

0x7e002000 INTE_UNK_0x0
0x7e002004 INTE_UNK_0x4
0x7e002008 INTE_UNK_0x8
0x7e00200c INTE_UNK_0xc
0x7e002010 INTE_UNK_0x10
0x7e002014 INTE_UNK_0x14
0x7e002018 INTE_UNK_0x18
0x7e00201c INTE_UNK_0x1c
0x7e002020 INTE_UNK_0x20
0x7e002024 INTE_UNK_0x24
0x7e002028 INTE_UNK_0x28
0x7e00202c INTE_UNK_0x2c
0x7e002034 INTE_UNK_0x34
0x7e002038 INTE_UNK_0x38
0x7e002040 INTE_UNK_0x40
0x7e002044 INTE_UNK_0x44

Description

Details

Interrupt table address (INTE_TABLE_PTR)

0x7e002030 INTE_TABLE_PTR Interrupt table address

Description

Write the address of the interrupt vector here to enable interrupts.

Details

TIMER: System Timers

Description

TBD

Registers

Address Access Name Description
0x7e003000 ? TIMER_CS Control/Status
0x7e003004 ? TIMER_CLO Free Running Counter (Lower 32 Bits)
0x7e003008 ? TIMER_CHI Free Running Counter (Higher 32 Bits)
0x7e00300c ? TIMER_C0 Compare 0
0x7e003010 ? TIMER_C1 Compare 1
0x7e003014 ? TIMER_C2 Compare 2
0x7e003018 ? TIMER_C3 Compare 3

Control/Status (TIMER_CS)

0x7e003000 TIMER_CS Control/Status

Description

Details

Bits Name Description Access
3 M3 ?
2 M2 ?
1 M1 ?
0 M0 ?

Free Running Counter (Lower 32 Bits) (TIMER_CLO)

0x7e003004 TIMER_CLO Free Running Counter (Lower 32 Bits)

Description

Details

Free Running Counter (Higher 32 Bits) (TIMER_CHI)

0x7e003008 TIMER_CHI Free Running Counter (Higher 32 Bits)

Description

Details

Compare 0 (TIMER_C0)

0x7e00300c TIMER_C0 Compare 0

Description

Details

Compare 1 (TIMER_C1)

0x7e003010 TIMER_C1 Compare 1

Description

Details

Compare 2 (TIMER_C2)

0x7e003014 TIMER_C2 Compare 2

Description

Details

Compare 3 (TIMER_C3)

0x7e003018 TIMER_C3 Compare 3

Description

Details

DMA: DMA0-14

Description

TBD. This is very imcomplete, the official bcm2835 documentation contains a complete overview!

Registers

Address Access Name Description
0x7e007000+i*0x100 R/W DMA_CHAN_[0-14]_CS Control and Status

Control and Status (DMA_CHAN_[0-14]_CS)

0x7e007000+i*0x100 DMA_CHAN_[0-14]_CS Control and Status

Description

Details

Bits Name Description Access
31 RESET W
30 ABORT W
29 DISDEBUG R/W
28 WAIT R/W
23-20 PANIC_PRIO R/W
19-16 PRIORITY R/W
8 ERROR Indicates whether the DMA channel has detected an error.
Value Name Description
0x0 OK The channel is ok.
0x1 ERROR An error flag is set.
R
6 WAIT_STATUS R
5 DREQ_STOPS_DMA R
4 PAUSED R
3 DREQ R
2 INT R/W
1 END R/W
0 ACTIVE R/W

PM: Power Management

Description

Power Management, Reset Controller and Watchdog registers.

Registers

Address Access Name Description
0x7e10001c ? PM_RSTC Reset control?
0x7e100020 ? PM_RSTS Reset status?
0x7e100024 ? PM_WDOG Watchdog timer counter

Reset control? (PM_RSTC)

0x7e10001c PM_RSTC Reset control?

Description

Details

Bits Name Description Access
31-24 UNK_24
Value Name Description
0x5a PASSWORD
?
8 RESET2 ?
5-4 WRCFG
Value Name Description
0x0 CLR
0x1 SET
0x2 FULL_RESET
?
1 RESET1 ?

Reset status? (PM_RSTS)

0x7e100020 PM_RSTS Reset status?

Description

Details

Bits Name Description Access
12 HADPOR ?
10 HADSRH ?
9 HADSRF ?
8 HADSRQ ?
6 HADWRH ?
5 HADWRF ?
4 HADWRQ ?
2 HADDRH ?
1 HADDRF ?
0 HADDRQ ?

Watchdog timer counter (PM_WDOG)

0x7e100024 PM_WDOG Watchdog timer counter

Description

Details

Bits Name Description Access
31-24 UNK_24
Value Name Description
0x5a PASSWORD
?
19-0 TIME_SET Number of ticks after which the watchdog timer expires. ?

CM: Clock Management

Description

The BCM2835 system has a number of clocks for the various components which are driven either by a PLL or the external 19.2 MHz oscillator. Known clocks are the core clock (CM_VPU), the system timer clock (PM_TIME) which controls the speed of the system timer and the GPIO clocks which are documented in the Raspberry Pi peripheral documentation. The interactions between the clocks are mostly unknown. The core clock affects at least execution speed on the videocore processor and the speed of the mini uart.

Registers

Address Access Name Description
0x7e101008 R/W CM_VPU_CTL Clock Control
0x7e10100c R/W CM_VPU_DIV Clock Divisor
0x7e101028 R/W CM_H264_CTL Clock Control
0x7e10102c R/W CM_H264_DIV Clock Divisor
0x7e101030 R/W CM_UNK_0x30_CTL Clock Control
0x7e101034 R/W CM_UNK_0x30_DIV Clock Divisor
0x7e101038 R/W CM_V3D_CTL Clock Control
0x7e10103c R/W CM_V3D_DIV Clock Divisor
0x7e101040 R/W CM_CAM0_LP_CTL Clock Control
0x7e101044 R/W CM_CAM0_LP_DIV Clock Divisor
0x7e101058 R/W CM_DSI0_ESC_CTL/CM_DSI1_ESC_CTL Clock Control
0x7e10105c R/W CM_DSI0_ESC_DIV/CM_DSI1_ESC_DIV Clock Divisor
0x7e101068 R/W CM_DPI_CTL Clock Control
0x7e10106c R/W CM_DPI_DIV Clock Divisor
0x7e101070+i*0x8 R/W CM_GP[0-2]_CTL Clock Control
0x7e101074+i*0x8 R/W CM_GP[0-2]_DIV Clock Divisor
0x7e101088 R/W CM_HSM_CTL Clock Control
0x7e10108c R/W CM_HSM_DIV Clock Divisor
0x7e101090 R/W CM_ISP_CTL Clock Control
0x7e101094 R/W CM_ISP_DIV Clock Divisor
0x7e101098 R/W CM_PCM_CTL Clock Control
0x7e10109c R/W CM_PCM_DIV Clock Divisor
0x7e1010a0 R/W CM_PWM_CTL Clock Control
0x7e1010a4 R/W CM_PWM_DIV Clock Divisor
0x7e1010a8 R/W CM_SLIM_CTL Clock Control
0x7e1010ac R/W CM_SLIM_DIV Clock Divisor
0x7e1010b0 R/W CM_SMI_CTL Clock Control
0x7e1010b4 R/W CM_SMI_DIV Clock Divisor
0x7e1010c0 R/W CM_eMMC_CTL Clock Control
0x7e1010c4 R/W CM_eMMC_DIV Clock Divisor
0x7e1010e0 R/W CM_TSENS_CTL Clock Control
0x7e1010e4 R/W CM_TSENS_DIV Clock Divisor
0x7e1010e8 R/W CM_TIME_CTL Clock Control
0x7e1010ec R/W CM_TIME_DIV Clock Divisor
0x7e1010f0 R/W CM_UART_CTL Clock Control
0x7e1010f4 R/W CM_UART_DIV Clock Divisor
0x7e1010f8 R/W CM_VEC_CTL Clock Control
0x7e1010fc R/W CM_VEC_DIV Clock Divisor
0x7e101190 R/W CM_UNK_0x190_CTL Clock Control
0x7e101194 R/W CM_UNK_0x190_DIV Clock Divisor
0x7e1011b0 R/W CM_ARM_CTL Clock Control
0x7e1011b4 R/W CM_ARM_DIV Clock Divisor
0x7e1011c0 R/W CM_UNK_0x1c0_CTL Clock Control
0x7e1011c4 R/W CM_UNK_0x1c0_DIV Clock Divisor

Clock Control Registers

0x7e101008 CM_VPU_CTL Clock Control
0x7e101028 CM_H264_CTL Clock Control
0x7e101030 CM_UNK_0x30_CTL Clock Control
0x7e101038 CM_V3D_CTL Clock Control
0x7e101040 CM_CAM0_LP_CTL Clock Control
0x7e101058 CM_DSI0_ESC_CTL/CM_DSI1_ESC_CTL Clock Control
0x7e101068 CM_DPI_CTL Clock Control
0x7e101070+i*0x8 CM_GP[0-2]_CTL Clock Control
0x7e101088 CM_HSM_CTL Clock Control
0x7e101090 CM_ISP_CTL Clock Control
0x7e101098 CM_PCM_CTL Clock Control
0x7e1010a0 CM_PWM_CTL Clock Control
0x7e1010a8 CM_SLIM_CTL Clock Control
0x7e1010b0 CM_SMI_CTL Clock Control
0x7e1010c0 CM_eMMC_CTL Clock Control
0x7e1010e0 CM_TSENS_CTL Clock Control
0x7e1010e8 CM_TIME_CTL Clock Control
0x7e1010f0 CM_UART_CTL Clock Control
0x7e1010f8 CM_VEC_CTL Clock Control
0x7e101190 CM_UNK_0x190_CTL Clock Control
0x7e1011b0 CM_ARM_CTL Clock Control
0x7e1011c0 CM_UNK_0x1c0_CTL Clock Control

Description

Details

Bits Name Description Access
31-24 PASSWD
Value Name Description
0x5a PASSWD
W
10-9 MASH ?
8 FLIP ?
7 BUSY ?
5 KILL ?
3-0 SRC
Value Name Description
0x0 GND
0x1 OSC External oscillator
0x4 PLLA
0x5 PLLC
0x6 PLLD
0x7 HDMI
R/W

Clock Divisor Registers

0x7e10100c CM_VPU_DIV Clock Divisor
0x7e10102c CM_H264_DIV Clock Divisor
0x7e101034 CM_UNK_0x30_DIV Clock Divisor
0x7e10103c CM_V3D_DIV Clock Divisor
0x7e101044 CM_CAM0_LP_DIV Clock Divisor
0x7e10105c CM_DSI0_ESC_DIV/CM_DSI1_ESC_DIV Clock Divisor
0x7e10106c CM_DPI_DIV Clock Divisor
0x7e101074+i*0x8 CM_GP[0-2]_DIV Clock Divisor
0x7e10108c CM_HSM_DIV Clock Divisor
0x7e101094 CM_ISP_DIV Clock Divisor
0x7e10109c CM_PCM_DIV Clock Divisor
0x7e1010a4 CM_PWM_DIV Clock Divisor
0x7e1010ac CM_SLIM_DIV Clock Divisor
0x7e1010b4 CM_SMI_DIV Clock Divisor
0x7e1010c4 CM_eMMC_DIV Clock Divisor
0x7e1010e4 CM_TSENS_DIV Clock Divisor
0x7e1010ec CM_TIME_DIV Clock Divisor
0x7e1010f4 CM_UART_DIV Clock Divisor
0x7e1010fc CM_VEC_DIV Clock Divisor
0x7e101194 CM_UNK_0x190_DIV Clock Divisor
0x7e1011b4 CM_ARM_DIV Clock Divisor
0x7e1011c4 CM_UNK_0x1c0_DIV Clock Divisor

Description

The resulting clock is the source divided by (DIVI + DIVF / 1024).

Details

Bits Name Description Access
31-24 PASSWD
Value Name Description
0x5a PASSWD
W
23-12 DIVI Integer part ?
11-0 DIVF Fractional part ?

A2W:

Description

The A2W register region seems to contain at least the settings of the various PLLs used for clock generation. The peripheral document lists a number of clock sources in the section about GPIO clock generation.

Per default, the videocore processor uses the PLLC while the ARM core uses the PLLA and other components use the PLLD.

Some information is available at http://elinux.org/RPi_Overclocking. TBD

Registers

Address Access Name Description
0x7e102020 R/W A2W_PLLC_MULT PLL Multiplier
0x7e102024 ? A2W_PLLC_UNK_0x24
0x7e102028 ? A2W_PLLC_UNK_0x28
0x7e10202c ? A2W_PLLC_UNK_0x2c
0x7e102030 ? A2W_PLLC_UNK_0x30
0x7e102034 ? A2W_PLLC_UNK_0x34
0x7e102038 ? A2W_PLLC_UNK_0x38
0x7e10203c ? A2W_PLLC_UNK_0x3c
0x7e102040 R/W A2W_PLLD_MULT PLL Multiplier
0x7e102044 ? A2W_PLLD_UNK_0x44
0x7e102048 ? A2W_PLLD_UNK_0x48
0x7e10204c ? A2W_PLLD_UNK_0x4c
0x7e102050 ? A2W_PLLD_UNK_0x50
0x7e102054 ? A2W_PLLD_UNK_0x54
0x7e102058 ? A2W_PLLD_UNK_0x58
0x7e10205c ? A2W_PLLD_UNK_0x5c
0x7e1020e0 R/W A2W_PLLA_MULT PLL Multiplier
0x7e1020e4 ? A2W_PLLA_UNK_0xe4
0x7e1020e8 ? A2W_PLLA_UNK_0xe8
0x7e1020ec ? A2W_PLLA_UNK_0xec
0x7e1020f0 ? A2W_PLLA_UNK_0xf0
0x7e1020f4 ? A2W_PLLA_UNK_0xf4
0x7e1020f8 ? A2W_PLLA_UNK_0xf8
0x7e1020fc ? A2W_PLLA_UNK_0xfc
0x7e102120 R/W A2W_PLLC_MULT2 PLL Multiplier 2 (?)
0x7e102140 R/W A2W_PLLD_MULT2 PLL Multiplier 2 (?)
0x7e1021e0 R/W A2W_PLLA_MULT2 PLL Multiplier 2 (?)
0x7e102220 R/W A2W_PLLC_MULT_FRACT Fractional Part
0x7e102240 R/W A2W_PLLD_MULT_FRACT Fractional Part
0x7e1022e0 R/W A2W_PLLA_MULT_FRACT Fractional Part
0x7e102620 ? A2W_PLLx_DIV PLL divisor

PLL Multiplier

0x7e102020 A2W_PLLC_MULT PLL Multiplier
0x7e102040 A2W_PLLD_MULT PLL Multiplier
0x7e1020e0 A2W_PLLA_MULT PLL Multiplier
0x7e102120 A2W_PLLC_MULT2 PLL Multiplier 2 (?)
0x7e102140 A2W_PLLD_MULT2 PLL Multiplier 2 (?)
0x7e1021e0 A2W_PLLA_MULT2 PLL Multiplier 2 (?)

Description

Details

Bits Name Description Access
31-24 PASSWD
Value Name Description
0x5a PASSWD
?
11-0 MULT ?

A2W_PLLC_UNK_0x24

0x7e102024 A2W_PLLC_UNK_0x24

Description

Details

A2W_PLLC_UNK_0x28

0x7e102028 A2W_PLLC_UNK_0x28

Description

Details

A2W_PLLC_UNK_0x2c

0x7e10202c A2W_PLLC_UNK_0x2c

Description

Details

A2W_PLLC_UNK_0x30

0x7e102030 A2W_PLLC_UNK_0x30

Description

Details

A2W_PLLC_UNK_0x34

0x7e102034 A2W_PLLC_UNK_0x34

Description

Details

A2W_PLLC_UNK_0x38

0x7e102038 A2W_PLLC_UNK_0x38

Description

Details

A2W_PLLC_UNK_0x3c

0x7e10203c A2W_PLLC_UNK_0x3c

Description

Details

A2W_PLLD_UNK_0x44

0x7e102044 A2W_PLLD_UNK_0x44

Description

Details

A2W_PLLD_UNK_0x48

0x7e102048 A2W_PLLD_UNK_0x48

Description

Details

A2W_PLLD_UNK_0x4c

0x7e10204c A2W_PLLD_UNK_0x4c

Description

Details

A2W_PLLD_UNK_0x50

0x7e102050 A2W_PLLD_UNK_0x50

Description

Details

A2W_PLLD_UNK_0x54

0x7e102054 A2W_PLLD_UNK_0x54

Description

Details

A2W_PLLD_UNK_0x58

0x7e102058 A2W_PLLD_UNK_0x58

Description

Details

A2W_PLLD_UNK_0x5c

0x7e10205c A2W_PLLD_UNK_0x5c

Description

Details

A2W_PLLA_UNK_0xe4

0x7e1020e4 A2W_PLLA_UNK_0xe4

Description

Details

A2W_PLLA_UNK_0xe8

0x7e1020e8 A2W_PLLA_UNK_0xe8

Description

Details

A2W_PLLA_UNK_0xec

0x7e1020ec A2W_PLLA_UNK_0xec

Description

Details

A2W_PLLA_UNK_0xf0

0x7e1020f0 A2W_PLLA_UNK_0xf0

Description

Details

A2W_PLLA_UNK_0xf4

0x7e1020f4 A2W_PLLA_UNK_0xf4

Description

Details

A2W_PLLA_UNK_0xf8

0x7e1020f8 A2W_PLLA_UNK_0xf8

Description

Details

A2W_PLLA_UNK_0xfc

0x7e1020fc A2W_PLLA_UNK_0xfc

Description

Details

PLL Multiplier (Fractional Part) (A2W_PLLC_MULT_FRACT, A2W_PLLD_MULT_FRACT, A2W_PLLA_MULT_FRACT)

0x7e102220 A2W_PLLC_MULT_FRACT Fractional Part
0x7e102240 A2W_PLLD_MULT_FRACT Fractional Part
0x7e1022e0 A2W_PLLA_MULT_FRACT Fractional Part

Description

Details

Bits Name Description Access
31-24 PASSWD
Value Name Description
0x5a PASSWD
?
19-0 MULT_FRACT ?

PLL divisor (A2W_PLLx_DIV)

0x7e102620 A2W_PLLx_DIV PLL divisor

Description

Divisor of PLLs, at least of PLLC

Details

Bits Name Description Access
31-24 PASSWD
Value Name Description
0x5a PASSWD
?
23-0 DIV ?

AVS: Audio Video Standard

Description

TBD (http://en.wikipedia.org/wiki/Audio_Video_Standard)

Registers

Address Access Name Description

RNG: Random Number Generator

Description

A hardware random number generator which measures thermal noise to produce random numbers. A driver for this exists in the linux tree, although no other documentation has been released.

Registers

Address Access Name Description
0x7e104000 ? RNG_CTRL RNG control register
0x7e104004 ? RNG_STATUS RNG status (available word count)
0x7e104008 ? RNG_DATA Random number output
0x7e10400c ? RNG_FF_THRESHOLD

RNG control register (RNG_CTRL)

0x7e104000 RNG_CTRL RNG control register

Description

Details

Bits Name Description Access
1 RBG2X Writing a 1 here doubles the rate of random numbers, but decreases the "randomness". ?
0 RBGEN Writing a 1 enables the RNG, writing a 0 disables it. ?

RNG status (available word count) (RNG_STATUS)

0x7e104004 RNG_STATUS RNG status (available word count)

Description

Details

Bits Name Description Access
31-24 AVAIL_COUNT Number of bytes available through the DATA register. ?
23-0 SKIP Writing a number here makes the RNG skip the number of words. Linux writes 0x40000 here at initialization to skip some words until "randomness" is high enough. ?

Random number output (RNG_DATA)

0x7e104008 RNG_DATA Random number output

Description

If STATUS.AVAIL_COUNT is greater than 0, a 32-bit random word can be read from this register.

Details

RNG_FF_THRESHOLD

0x7e10400c RNG_FF_THRESHOLD

Description

Details

GPIO: General Purpose IO

Description

TBD

Registers

Address Access Name Description
0x7e200000 ? GPIO_FSEL0
0x7e200004 ? GPIO_FSEL1
0x7e200008 ? GPIO_FSEL2
0x7e20000c ? GPIO_FSEL3
0x7e200010 ? GPIO_FSEL4
0x7e200014 ? GPIO_FSEL5
0x7e20001c ? GPIO_SET0
0x7e200020 ? GPIO_SET1
0x7e200028 ? GPIO_CLR0
0x7e20002c ? GPIO_CLR1
0x7e200034 ? GPIO_LEV0
0x7e200038 ? GPIO_LEV1
0x7e200094 ? GPIO_PUD
0x7e200098 ? GPIO_PUDCLK0
0x7e20009c ? GPIO_PUDCLK1

GPIO_FSEL0

0x7e200000 GPIO_FSEL0

Description

Details

Bits Name Description Access
29-27 FSEL9
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 SPI0_MISO
0x3 SD1
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 AUX5
R/W
26-24 FSEL8
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 SPI0_CE0_N
0x3 SD0
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 AUX5
R/W
23-21 FSEL7
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 SPI0_CE1_N
0x3 SWE_N
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 AUX5
R/W
20-18 FSEL6
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 GPCLK2
0x3 SOE_N
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 ARM_RTCK
R/W
17-15 FSEL5
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 GPCLK1
0x3 SA0
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 ARM_TDO
R/W
14-12 FSEL4
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 GPCLK0
0x3 SA1
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 ARM_TDI
R/W
11-9 FSEL3
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 SCL1
0x3 SA2
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 AUX5
R/W
8-6 FSEL2
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 SDA1
0x3 SA3
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 AUX5
R/W
5-3 FSEL1
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 SCL0
0x3 SA4
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 AUX5
R/W
2-0 FSEL0
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 SDA0
0x3 SA5
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 AUX5
R/W

GPIO_FSEL1

0x7e200004 GPIO_FSEL1

Description

Details

Bits Name Description Access
29-27 FSEL19
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 PCM_FS
0x3 SD11
0x4 AUX2
0x5 BSCSL_SCL
0x6 SPI1_MISO
0x7 PWM1
R/W
26-24 FSEL18
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 PCM_CLK
0x3 SD10
0x4 AUX2
0x5 BCSCL_SDA
0x6 SPI1_CE0_N
0x7 PWM0
R/W
23-21 FSEL17
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 AUX0
0x3 SD9
0x4 AUX2
0x5 RTS0
0x6 SPI1_CE1_N
0x7 RTS1
R/W
20-18 FSEL16
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 AUX0
0x3 SD8
0x4 AUX2
0x5 CTS0
0x6 SPI1_CE2_N
0x7 CTS1
R/W
17-15 FSEL15
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 RXD0
0x3 SD7
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 RXD1
R/W
14-12 FSEL14
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 TXD0
0x3 SD6
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 TXD1
R/W
11-9 FSEL13
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 PWM1
0x3 SD5
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 ARM_TCK
R/W
8-6 FSEL12
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 PWM0
0x3 SD4
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 ARM_TMS
R/W
5-3 FSEL11
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 SPI0_SCLK
0x3 SD2
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 AUX5
R/W
2-0 FSEL10
Value Name Description
0x0 INPUT
0x1 OUTPUT
0x2 SPI0_MOSI
0x3 SD2
0x4 AUX2
0x5 AUX3
0x6 AUX4
0x7 AUX5
R/W

GPIO_FSEL2

0x7e200008 GPIO_FSEL2

Description

Details

GPIO_FSEL3

0x7e20000c GPIO_FSEL3

Description

Details

GPIO_FSEL4

0x7e200010 GPIO_FSEL4

Description

Details

GPIO_FSEL5

0x7e200014 GPIO_FSEL5

Description

Details

GPIO_SET0

0x7e20001c GPIO_SET0

Description

Details

GPIO_SET1

0x7e200020 GPIO_SET1

Description

Details

GPIO_CLR0

0x7e200028 GPIO_CLR0

Description

Details

GPIO_CLR1

0x7e20002c GPIO_CLR1

Description

Details

GPIO_LEV0

0x7e200034 GPIO_LEV0

Description

Details

GPIO_LEV1

0x7e200038 GPIO_LEV1

Description

Details

GPIO_PUD

0x7e200094 GPIO_PUD

Description

Details

GPIO_PUDCLK0

0x7e200098 GPIO_PUDCLK0

Description

Details

GPIO_PUDCLK1

0x7e20009c GPIO_PUDCLK1

Description

Details

ALTMMC: Alternate MMC

Description

Alternate interface to MMC/SD cards. This is used by bootcode.bin to load the next executable from the SD card.

Registers

Address Access Name Description
0x7e202000 ? ALTMMC_CMD Command
0x7e202004 ? ALTMMC_ARG Argument
0x7e202008 ? ALTMMC_TIMEOUT Timeout
0x7e20200c ? ALTMMC_CLKDIV ClkDiv
0x7e202010 ? ALTMMC_RSP0 Response 0
0x7e202014 ? ALTMMC_RSP1 Response 1
0x7e202018 ? ALTMMC_RSP2 Response 2
0x7e20201c ? ALTMMC_RSP3 Response 3
0x7e202020 ? ALTMMC_STATUS Status
0x7e202024 ? ALTMMC_UNK_0x24
0x7e202028 ? ALTMMC_UNK_0x28
0x7e20202c ? ALTMMC_UNK_0x2c
0x7e202030 ? ALTMMC_VDD
0x7e202034 ? ALTMMC_EDM
0x7e202038 ? ALTMMC_HOST_CFG Host Config
0x7e20203c ? ALTMMC_HBCT Bytecount
0x7e202040 ? ALTMMC_DATA
0x7e202044 ? ALTMMC_UNK_0x44
0x7e202048 ? ALTMMC_UNK_0x48
0x7e20204c ? ALTMMC_UNK_0x4c
0x7e202050 ? ALTMMC_HBLC Blockcount

Command (ALTMMC_CMD)

0x7e202000 ALTMMC_CMD Command

Description

Details

Bits Name Description Access
15 ENABLE Set this to 1 to when executing a command, it will reset itself to 0 when the command has finished executing. R/W
14 FAIL ?
11 BUSY Set this to zero when executing TRANSFER_STOP or one when executing READ_MULTIPLE_BLOCKS ?/W
10 NO_RSP No Response ?
9 LONG_RSP Long Response ?
7 WRITE ?
6 READ ?
5-0 CMD The command according to the MMC spec. ?/W

Argument (ALTMMC_ARG)

0x7e202004 ALTMMC_ARG Argument

Description

The argument should be written here before the command is written to 0x0

Details

Timeout (ALTMMC_TIMEOUT)

0x7e202008 ALTMMC_TIMEOUT Timeout

Description

Details

ClkDiv (ALTMMC_CLKDIV)

0x7e20200c ALTMMC_CLKDIV ClkDiv

Description

Set to 0x19

Details

Response 0 (ALTMMC_RSP0)

0x7e202010 ALTMMC_RSP0 Response 0

Description

Details

Response 1 (ALTMMC_RSP1)

0x7e202014 ALTMMC_RSP1 Response 1

Description

Details

Response 2 (ALTMMC_RSP2)

0x7e202018 ALTMMC_RSP2 Response 2

Description

Details

Response 3 (ALTMMC_RSP3)

0x7e20201c ALTMMC_RSP3 Response 3

Description

Details

Status (ALTMMC_STATUS)

0x7e202020 ALTMMC_STATUS Status

Description

Details

Bits Name Description Access
31-1 UNKNOWN Bits 7:5 and 3 are sometimes returned from a function. ?
0 FIFO_STATUS Set when there is data in the FIFO (Data Register 0x40) R

Unknown Registers

0x7e202024 ALTMMC_UNK_0x24
0x7e20202c ALTMMC_UNK_0x2c
0x7e202044 ALTMMC_UNK_0x44
0x7e202048 ALTMMC_UNK_0x48
0x7e20204c ALTMMC_UNK_0x4c

Description

Details

ALTMMC_UNK_0x28

0x7e202028 ALTMMC_UNK_0x28

Description

Set to 1

Details

ALTMMC_VDD

0x7e202030 ALTMMC_VDD

Description

Details

ALTMMC_EDM

0x7e202034 ALTMMC_EDM

Description

Details

Host Config (ALTMMC_HOST_CFG)

0x7e202038 ALTMMC_HOST_CFG Host Config

Description

Set to 0xA

Details

Bytecount (ALTMMC_HBCT)

0x7e20203c ALTMMC_HBCT Bytecount

Description

Details

ALTMMC_DATA

0x7e202040 ALTMMC_DATA

Description

Data from the MMC card can be read from this FIFO 4 bytes at a time.

Details

Blockcount (ALTMMC_HBLC)

0x7e202050 ALTMMC_HBLC Blockcount

Description

Details

OTP0: One Time Programmable Memory

Description

Not accessible via the ARM core.

This is an (undocumented) interface to the OTP (unofficially codenamed Dragon) used by bootcode.bin (and probably other parts of the bootchain.) It appears to start repeating after the 128th word. 0x80 == 0x00, 0x81 = 0x01 and so forth. This gives us an OTP storage of 128 words[32 bit] or 512 bytes.

Here is code for generating a bootcode.bin for dumping the contents of your OTP over serial: https://gist.github.com/3972820.

Registers

Address Access Name Description
0x7e20f000 ? OTP0_UNK_0x0
0x7e20f004 ? OTP0_UNK_0x4
0x7e20f008 ? OTP0_UNK_0x8
0x7e20f00c ? OTP0_UNK_0xc
0x7e20f010 ? OTP0_UNK_0x10
0x7e20f014 ? OTP0_UNK_0x14
0x7e20f018 ? OTP0_UNK_0x18
0x7e20f01c ? OTP0_UNK_0x1c
0x7e20f020 ? OTP0_UNK_0x20
0x7e20f024 ? OTP0_UNK_0x24

Unknown Registers

0x7e20f000 OTP0_UNK_0x0
0x7e20f004 OTP0_UNK_0x4
0x7e20f008 OTP0_UNK_0x8
0x7e20f00c OTP0_UNK_0xc
0x7e20f010 OTP0_UNK_0x10
0x7e20f014 OTP0_UNK_0x14
0x7e20f018 OTP0_UNK_0x18
0x7e20f01c OTP0_UNK_0x1c
0x7e20f020 OTP0_UNK_0x20
0x7e20f024 OTP0_UNK_0x24

Description

Details

SLIM: SLIMbus

Description

TBD. http://en.wikipedia.org/wiki/SLIMbus

Registers

Address Access Name Description

UNK212000:

Description

TBD - Needs confirmation, all I got was 0x448

Registers

Address Access Name Description

AUX: Auxiliaries

Description

UART1, SPI1 and SPI2

Registers

Address Access Name Description
0x7e215000 ? AUX_IRQ
0x7e215004 ? AUX_ENABLES
0x7e215040 ? AUX_MU_IO_REG
0x7e215044 ? AUX_MU_IER_REG
0x7e215048 ? AUX_MU_IIR_REG
0x7e21504c ? AUX_MU_LCR_REG
0x7e215050 ? AUX_MU_MCR_REG
0x7e215054 ? AUX_MU_LSR_REG
0x7e215058 ? AUX_MU_SR_REG
0x7e21505c ? AUX_MU_SCRATCH
0x7e215060 ? AUX_MU_CNTL_REG
0x7e215064 ? AUX_MU_STAT_REG
0x7e215068 ? AUX_MU_BAUD_REG

AUX_IRQ

0x7e215000 AUX_IRQ

Description

Details

Bits Name Description Access
2 SPI_2 ?
1 SPI_1 ?
0 UART ?

AUX_ENABLES

0x7e215004 AUX_ENABLES

Description

Details

Bits Name Description Access
2 SPI_2 ?
1 SPI_1 ?
0 UART ?

AUX_MU_IO_REG

0x7e215040 AUX_MU_IO_REG

Description

Details

AUX_MU_IER_REG

0x7e215044 AUX_MU_IER_REG

Description

Details

AUX_MU_IIR_REG

0x7e215048 AUX_MU_IIR_REG

Description

Details

AUX_MU_LCR_REG

0x7e21504c AUX_MU_LCR_REG

Description

Details

AUX_MU_MCR_REG

0x7e215050 AUX_MU_MCR_REG

Description

Details

AUX_MU_LSR_REG

0x7e215054 AUX_MU_LSR_REG

Description

Details

Bits Name Description Access
6 TX_IDLE ?
5 TX_EMPTY ?
1 RX_OVER ?
0 RX_READY ?

AUX_MU_SR_REG

0x7e215058 AUX_MU_SR_REG

Description

Details

AUX_MU_SCRATCH

0x7e21505c AUX_MU_SCRATCH

Description

Details

AUX_MU_CNTL_REG

0x7e215060 AUX_MU_CNTL_REG

Description

Details

AUX_MU_STAT_REG

0x7e215064 AUX_MU_STAT_REG

Description

Details

AUX_MU_BAUD_REG

0x7e215068 AUX_MU_BAUD_REG

Description

Details

BSC2: BSC2

Description

TBD. Used for HDMI interface.

Registers

Address Access Name Description

L2CC: Level 2 Cache Controller

Description

TBD

Registers

Address Access Name Description
0x7ee01000 ? L2CC_UNK_0x0
0x7ee01004 ? L2CC_UNK_0x4
0x7ee01008 ? L2CC_UNK_0x8

Unknown Registers (L2CC_UNK_0x0, L2CC_UNK_0x4, L2CC_UNK_0x8)

0x7ee01000 L2CC_UNK_0x0
0x7ee01004 L2CC_UNK_0x4
0x7ee01008 L2CC_UNK_0x8

Description

Details

L1CC: Level 1 Cache Controller

Description

TBD

Registers

Address Access Name Description
0x7ee02000 ? L1CC_UNK_0x0
0x7ee02080 ? L1CC_UNK_0x80
0x7ee02104 ? L1CC_UNK_0x104
0x7ee02108 ? L1CC_UNK_0x108

Unknown Registers (L1CC_UNK_0x0, L1CC_UNK_0x80, L1CC_UNK_0x104, L1CC_UNK_0x108)

0x7ee02000 L1CC_UNK_0x0
0x7ee02080 L1CC_UNK_0x80
0x7ee02104 L1CC_UNK_0x104
0x7ee02108 L1CC_UNK_0x108

Description

Details