• Register Documentation
• List of MMIO Regions
• MULT: Multicore Sync Block
• Description
• Registers
• INTE: VC Interrupt Controller
• Description
• Registers
• Unknown Registers
• Description
• Details
• Interrupt table address (INTE_TABLE_PTR)
• Description
• Details
• TIMER: System Timers
• Description
• Registers
• Control/Status (TIMER_CS)
• Description
• Details
• Free Running Counter (Lower 32 Bits) (TIMER_CLO)
• Description
• Details
• Free Running Counter (Higher 32 Bits) (TIMER_CHI)
• Description
• Details
• Compare 0 (TIMER_C0)
• Description
• Details
• Compare 1 (TIMER_C1)
• Description
• Details
• Compare 2 (TIMER_C2)
• Description
• Details
• Compare 3 (TIMER_C3)
• Description
• Details
• DMA: DMA0-14
• Description
• Registers
• Control and Status (DMA_CHAN_[0-14]_CS)
• Description
• Details
• PM: Power Management
• Description
• Registers
• Reset control? (PM_RSTC)
• Description
• Details
• Reset status? (PM_RSTS)
• Description
• Details
• Watchdog timer counter (PM_WDOG)
• Description
• Details
• CM: Clock Management
• Description
• Registers
• Clock Control Registers
• Description
• Details
• Clock Divisor Registers
• Description
• Details
• A2W:
• Description
• Registers
• PLL Multiplier
• Description
• Details
• A2W_PLLC_UNK_0x24
• Description
• Details
• A2W_PLLC_UNK_0x28
• Description
• Details
• A2W_PLLC_UNK_0x2c
• Description
• Details
• A2W_PLLC_UNK_0x30
• Description
• Details
• A2W_PLLC_UNK_0x34
• Description
• Details
• A2W_PLLC_UNK_0x38
• Description
• Details
• A2W_PLLC_UNK_0x3c
• Description
• Details
• A2W_PLLD_UNK_0x44
• Description
• Details
• A2W_PLLD_UNK_0x48
• Description
• Details
• A2W_PLLD_UNK_0x4c
• Description
• Details
• A2W_PLLD_UNK_0x50
• Description
• Details
• A2W_PLLD_UNK_0x54
• Description
• Details
• A2W_PLLD_UNK_0x58
• Description
• Details
• A2W_PLLD_UNK_0x5c
• Description
• Details
• A2W_PLLA_UNK_0xe4
• Description
• Details
• A2W_PLLA_UNK_0xe8
• Description
• Details
• A2W_PLLA_UNK_0xec
• Description
• Details
• A2W_PLLA_UNK_0xf0
• Description
• Details
• A2W_PLLA_UNK_0xf4
• Description
• Details
• A2W_PLLA_UNK_0xf8
• Description
• Details
• A2W_PLLA_UNK_0xfc
• Description
• Details
• PLL Multiplier (Fractional Part) (A2W_PLLC_MULT_FRACT, A2W_PLLD_MULT_FRACT, A2W_PLLA_MULT_FRACT)
• Description
• Details
• PLL divisor (A2W_PLLx_DIV)
• Description
• Details
• AVS: Audio Video Standard
• Description
• Registers
• RNG: Random Number Generator
• Description
• Registers
• RNG control register (RNG_CTRL)
• Description
• Details
• RNG status (available word count) (RNG_STATUS)
• Description
• Details
• Random number output (RNG_DATA)
• Description
• Details
• RNG_FF_THRESHOLD
• Description
• Details
• GPIO: General Purpose IO
• Description
• Registers
• GPIO_FSEL0
• Description
• Details
• GPIO_FSEL1
• Description
• Details
• GPIO_FSEL2
• Description
• Details
• GPIO_FSEL3
• Description
• Details
• GPIO_FSEL4
• Description
• Details
• GPIO_FSEL5
• Description
• Details
• GPIO_SET0
• Description
• Details
• GPIO_SET1
• Description
• Details
• GPIO_CLR0
• Description
• Details
• GPIO_CLR1
• Description
• Details
• GPIO_LEV0
• Description
• Details
• GPIO_LEV1
• Description
• Details
• GPIO_PUD
• Description
• Details
• GPIO_PUDCLK0
• Description
• Details
• GPIO_PUDCLK1
• Description
• Details
• ALTMMC: Alternate MMC
• Description
• Registers
• Command (ALTMMC_CMD)
• Description
• Details
• Argument (ALTMMC_ARG)
• Description
• Details
• Timeout (ALTMMC_TIMEOUT)
• Description
• Details
• ClkDiv (ALTMMC_CLKDIV)
• Description
• Details
• Response 0 (ALTMMC_RSP0)
• Description
• Details
• Response 1 (ALTMMC_RSP1)
• Description
• Details
• Response 2 (ALTMMC_RSP2)
• Description
• Details
• Response 3 (ALTMMC_RSP3)
• Description
• Details
• Status (ALTMMC_STATUS)
• Description
• Details
• Unknown Registers
• Description
• Details
• ALTMMC_UNK_0x28
• Description
• Details
• ALTMMC_VDD
• Description
• Details
• ALTMMC_EDM
• Description
• Details
• Host Config (ALTMMC_HOST_CFG)
• Description
• Details
• Bytecount (ALTMMC_HBCT)
• Description
• Details
• ALTMMC_DATA
• Description
• Details
• Blockcount (ALTMMC_HBLC)
• Description
• Details
• OTP0: One Time Programmable Memory
• Description
• Registers
• Unknown Registers
• Description
• Details
• SLIM: SLIMbus
• Description
• Registers
• UNK212000:
• Description
• Registers
• AUX: Auxiliaries
• Description
• Registers
• AUX_IRQ
• Description
• Details
• AUX_ENABLES
• Description
• Details
• AUX_MU_IO_REG
• Description
• Details
• AUX_MU_IER_REG
• Description
• Details
• AUX_MU_IIR_REG
• Description
• Details
• AUX_MU_LCR_REG
• Description
• Details
• AUX_MU_MCR_REG
• Description
• Details
• AUX_MU_LSR_REG
• Description
• Details
• AUX_MU_SR_REG
• Description
• Details
• AUX_MU_SCRATCH
• Description
• Details
• AUX_MU_CNTL_REG
• Description
• Details
• AUX_MU_STAT_REG
• Description
• Details
• AUX_MU_BAUD_REG
• Description
• Details
• BSC2: BSC2
• Description
• Registers
• L2CC: Level 2 Cache Controller
• Description
• Registers
• Unknown Registers (L2CC_UNK_0x0, L2CC_UNK_0x4, L2CC_UNK_0x8)
• Description
• Details
• L1CC: Level 1 Cache Controller
• Description
• Registers
• Unknown Registers (L1CC_UNK_0x0, L1CC_UNK_0x80, L1CC_UNK_0x104, L1CC_UNK_0x108)
• Description
• Details