[LOADER] Started
[LOADER] Found Multiboot information at 0x9500
[LOADER] Found module: [0x110000 - 0x1ba0798]
[LOADER] Found an ELF module at 0x110000
[LOADER] This is a supported HermitCore Application
[LOADER] Found TLS starts at 0x47f948 (size 264 Bytes)
[LOADER] File Size: 2627113 Bytes
[LOADER] Mem Size:  2636352 Bytes
[LOADER] Use 2 large pages for the application.
[LOADER] Clear BSS from 0x481629 to 0x483a40
[LOADER] BootInfo located at 0x10d0e0
[LOADER] Use stack address 0x1f8000
[LOADER] Jumping to HermitCore Application Entry Point at 0x3E8450
[0][INFO] Welcome to HermitCore-rs 0.3.27
[0][INFO] Kernel starts at 0x200000
[0][INFO] BSS starts at 0x481640
[0][INFO] TLS starts at 0x47f948 (size 264 Bytes)
[0][DEBUG] Set CR0 to 0x8001003b
[0][DEBUG] Set CR4 to 0x50660
[0][DEBUG] Create new view to the kernel space
[0][DEBUG] Found PML4 at 0x109000
[0][INFO] Found Multiboot info at 0x9500
[0][INFO] Found cmdline at 0x10f03e (size 62)
[0][INFO] Total memory size: 127 MB
[0][INFO] A pure Rust application is running on top of HermitCore!
[0][INFO] Heap: size 106 MB, start address 0x600000
[0][INFO] Heap is located at 0x600000 -- 0x7000000 (0 Bytes unmapped)
[0][INFO] 
[0][INFO] ===================== PHYSICAL MEMORY FREE LIST ======================
[0][INFO] 0x00000007000000 - 0x00000007FDF000
[0][INFO] ======================================================================
[0][INFO] 
[0][INFO] 
[0][INFO] ================== KERNEL VIRTUAL MEMORY FREE LIST ===================
[0][INFO] 0x00000007000000 - 0x00800000000000
[0][INFO] ======================================================================
[0][INFO] 
[0][DEBUG] Got cmdline tokens as ["loader/target/x86_64-unknown-hermit-loader/debug/rusty-loader"]
[0][INFO] 
[0][INFO] ========================== CPU INFORMATION ===========================
[0][INFO] Model:                   QEMU Virtual CPU version 2.5+
[0][INFO] Frequency:               3600 MHz (from Measurement)
[0][INFO] SpeedStep Technology:    Not Available
[0][INFO] Features:                MMX SSE SSE2 SSE3 RDRAND MCE FXSR XSAVE RDTSCP CLFLUSH FSGSBASE 
[0][INFO] Physical Address Width:  40 bits
[0][INFO] Linear Address Width:    48 bits
[0][INFO] Supports 1GiB Pages:     No
[0][INFO] ======================================================================
[0][INFO] 
[0][INFO] HermitCore-rs booted on 2020-05-13 at 06:49:42
[0][DEBUG] Scanning PCI Busses 0 to 31
[0][DEBUG] Bar 0 @1237:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 1 @1237:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 2 @1237:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 3 @1237:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 4 @1237:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 5 @1237:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 0 @7000:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 1 @7000:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 2 @7000:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 3 @7000:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 4 @7000:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 5 @7000:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 0 @1111:1234 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 1 @1111:1234 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 2 @1111:1234 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 3 @1111:1234 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 4 @1111:1234 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 5 @1111:1234 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 0 @100e:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 2 @100e:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 3 @100e:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 4 @100e:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][DEBUG] Bar 5 @100e:8086 is memory mapped, but treated as IO mapped! this will cause errors later..
[0][INFO] 
[0][INFO] ======================== PCI BUS INFORMATION =========================
[0][INFO] 00:00 Host bridge [0600]: Intel Corporation 440FX - 82441FX PMC [Natoma] [8086:1237], iobase 
[0][INFO] 00:01 ISA bridge [0601]: Intel Corporation 82371SB PIIX3 ISA [Natoma/Triton II] [8086:7000], iobase 
[0][INFO] 00:02 VGA compatible controller [0300]: Unknown Vendor Unknown Device [1234:1111], iobase 0xfd000008 (size 0x1000000) 0xfebf0000 (size 0x1000) 
[0][INFO] 00:03 Ethernet controller [0200]: Intel Corporation 82540EM Gigabit Ethernet Controller [8086:100E], IRQ 11, iobase 0xfebc0000 (size 0x20000) 0xc000 (size 0x40) 
[0][INFO] ======================================================================
[0][INFO] 
[0][INFO] Found an ACPI revision 0 table at 0xF5A30 with OEM ID "BOCHS "
[0][DEBUG] Found ACPI table: FACP
[0][DEBUG] Found ACPI table: APIC
[0][DEBUG] Found ACPI table: HPET
[0][DEBUG] Found Processor Local APIC record: { acpi_processor_id: 0, apic_id: 0, flags: 1 }
[0][DEBUG] Found Processor Local APIC record: { acpi_processor_id: 1, apic_id: 1, flags: 1 }
[0][DEBUG] Found Processor Local APIC record: { acpi_processor_id: 2, apic_id: 2, flags: 1 }
[0][DEBUG] Found Processor Local APIC record: { acpi_processor_id: 3, apic_id: 3, flags: 1 }
[0][DEBUG] Found I/O APIC record: { id: 0, reserved: 0, address: 0xFEC00000, global_system_interrupt_base: 0 }
[0][DEBUG] Mapping IOAPIC at 0xFEC00000 to virtual address 0x7030000
[0][DEBUG] Mapping Local APIC at 0xFEE00000 to virtual address 0x7031000
[0][DEBUG] Calibrated APIC Timer with a counter value of 128 for 1 microsecond
[0][INFO] IOAPIC v32 has 24 entries
[0][INFO] Disable IOAPIC timer
[0][DEBUG] Creating idle task 0
[0][DEBUG] Using boot stack 0x1F8000
[0][DEBUG] IST0 is located at 0x7010000
[0][DEBUG] Initializing scheduler for core 0 with idle task 0
[0][DEBUG] SMP boot code is 231 bytes long
[0][DEBUG] Mapping SMP boot code to physical and virtual address 0x8000
[0][DEBUG] Set entry point for application processor to 0x3e8450
[0][DEBUG] Waking up CPU 1 with Local APIC ID 1
[0][DEBUG] Waiting for it to respond
[1][DEBUG] Set CR0 to 0x8001003b
[1][DEBUG] Set CR4 to 0x50660
[1][DEBUG] Creating idle task 1
[0][DEBUG] Waking up CPU 2 with Local APIC ID 2
[1][DEBUG] Using boot stack 0x7034000
[1][DEBUG] IST0 is located at 0x703C000
[1][DEBUG] Initializing scheduler for core 1 with idle task 1
[1][INFO] Entering idle loop for application processor
[0][DEBUG] Waiting for it to respond
[2][DEBUG] Set CR0 to 0x8001003b
[2][DEBUG] Set CR4 to 0x50660
[2][DEBUG] Creating idle task 2
[2][DEBUG] Using boot stack 0x705C000
[0][DEBUG] Waking up CPU 3 with Local APIC ID 3
[2][DEBUG] IST0 is located at 0x7064000
[2][DEBUG] Initializing scheduler for core 2 with idle task 2
[2][INFO] Entering idle loop for application processor
[0][DEBUG] Waiting for it to respond
[3][DEBUG] Set CR0 to 0x8001003b
[3][DEBUG] Set CR4 to 0x50660
[3][DEBUG] Creating idle task 3
[3][DEBUG] Using boot stack 0x7084000
[3][DEBUG] IST0 is located at 0x708C000
[0][INFO] 
[0][INFO] ===================== MULTIPROCESSOR INFORMATION =====================
[3][DEBUG] Initializing scheduler for core 3 with idle task 3
[0][INFO] APIC in use:             xAPIC
[3][INFO] Entering idle loop for application processor
[0][INFO] Initialized CPUs:        4
[0][INFO] ======================================================================
[0][INFO] 
[0][DEBUG] Creating new task 4
[0][DEBUG] Create stacks at 0x70AC000 with a size of 1088 KB
[0][DEBUG] Set up TLS at 0x71c0120, tdata_size 0x0, tls_size 0x108
[0][DEBUG] Creating task 4 with priority 2 on core 0
[0][DEBUG] Task is available.
[0][DEBUG] Switching task from 0 to 4 (stack 0x0 => 0x70BDF60)
[0][INFO] HermitCore is running on common system!
[0][DEBUG] Switching FPU owner from task 0 to 4
[0][DEBUG] Creating new task 5
[0][DEBUG] Create stacks at 0x71C1000 with a size of 1088 KB
[0][DEBUG] Set up TLS at 0x72d5120, tdata_size 0x0, tls_size 0x108
[0][DEBUG] Creating task 5 with priority 3 on core 0
[INFO] Spawn network thread with id 5
[0][DEBUG] Task with a higher priority is available.
[0][DEBUG] Switching task from 4 to 5 (stack 0x70BDF60 => 0x71D2F60)
[0][DEBUG] Switching FPU owner from task 4 to 5
[WARN] Ethernet interface not available
[0][DEBUG] Finishing task 5 with exit code 0
[0][DEBUG] Task is available.
[0][DEBUG] Switching task from 5 to 4 (stack 0x71D2F60 => 0x70BDE40)
[0][DEBUG] Switching FPU owner from task 5 to 4
[0][DEBUG] Deallocating stacks at 0x71C1000 with a size of 1088 KB
[3][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Deallocate TLS at 0x72d5000 (size 0x1000)
[1][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
Hello, world!
Test hello ... ok
argument[0] = {name}
Test print_argv ... ok
Test print_env ... ok
[0][DEBUG] Open /etc/hostname, 0, 0
[0][DEBUG] Opening file /etc/hostname FilePerms { write: false, creat: false, excl: false, trunc: false, append: false, directio: false, raw: 0, mode: 0 }
[0][INFO] Trying to open file on non-existing mount point 'etc'!
Test read_file ... failed!
[0][DEBUG] Open /tmp/foo.txt, 577, 1911
[0][DEBUG] Opening file /tmp/foo.txt FilePerms { write: true, creat: true, excl: false, trunc: true, append: false, directio: false, raw: 577, mode: 511 }
[0][INFO] Trying to open file on non-existing mount point 'tmp'!
Test create_file ... failed!
[0][DEBUG] Creating new task 6
[0][DEBUG] Create stacks at 0x71C1000 with a size of 1088 KB
[3][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Set up TLS at 0x72d5120, tdata_size 0x0, tls_size 0x108
[1][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Creating task 6 with priority 2 on core 1
[1][DEBUG] Received Wakeup Interrupt
[1][DEBUG] Task is available.
[1][DEBUG] Switching task from 1 to 6 (stack 0x0 => 0x71D2F60)
[0][DEBUG] Creating new task 7
[0][DEBUG] Create stacks at 0x72D6000 with a size of 1088 KB
[1][DEBUG] Switching FPU owner from task 1 to 6
this is thread number 0
[1][DEBUG] Finishing task 6 with exit code 0
[1][DEBUG] Only Idle Task is available.
[1][DEBUG] Switching task from 6 to 1 (stack 0x71D2F60 => 0x703BD50)
[1][DEBUG] Cleaning up task 6
[0][DEBUG] Set up TLS at 0x73ea120, tdata_size 0x0, tls_size 0x108
[0][DEBUG] Creating task 7 with priority 2 on core 2
[2][DEBUG] Received Wakeup Interrupt
[2][DEBUG] Task is available.
[2][DEBUG] Switching task from 2 to 7 (stack 0x0 => 0x72E7F60)
[2][DEBUG] Switching FPU owner from task 2 to 7
[0][DEBUG] Task 4 is waiting for task 6
this is thread number 1
[2][DEBUG] Finishing task 7 with exit code 0
[2][DEBUG] Only Idle Task is available.
[2][DEBUG] Switching task from 7 to 2 (stack 0x72E7F60 => 0x7063D50)
[2][DEBUG] Cleaning up task 7
[0][DEBUG] Task 4 is waiting for task 7
Test threading ... ok
Pi: 3.141592653589587 (sequential)
Test pi_sequential ... ok
[0][DEBUG] Creating new task 8
[0][DEBUG] Create stacks at 0x73EB000 with a size of 1088 KB
[0][DEBUG] Set up TLS at 0x74ff120, tdata_size 0x0, tls_size 0x108
[0][DEBUG] Creating task 8 with priority 2 on core 3
[3][DEBUG] Received Wakeup Interrupt
[3][DEBUG] Task is available.
[0][DEBUG] Creating new task 9
[3][DEBUG] Switching task from 3 to 8 (stack 0x0 => 0x73FCF60)
[0][DEBUG] Create stacks at 0x7500000 with a size of 1088 KB
[3][DEBUG] Switching FPU owner from task 3 to 8
[0][DEBUG] Set up TLS at 0x7614120, tdata_size 0x0, tls_size 0x108
[0][DEBUG] Creating task 9 with priority 2 on core 0
[0][DEBUG] Task 4 is waiting for task 8
[0][DEBUG] Blocking task 4
[0][DEBUG] Cleaning up task 5
[0][DEBUG] Task is available.
[0][DEBUG] Switching task from 4 to 9 (stack 0x70BDE40 => 0x7511F60)
[0][DEBUG] Switching FPU owner from task 4 to 9
[3][DEBUG] Finishing task 8 with exit code 0
[3][DEBUG] Only Idle Task is available.
[3][DEBUG] Switching task from 8 to 3 (stack 0x73FCF60 => 0x708BD50)
[3][DEBUG] Cleaning up task 8
[0][DEBUG] Received Wakeup Interrupt
[0][DEBUG] Waking up task 4 on core 0
[0][DEBUG] Finishing task 9 with exit code 0
[0][DEBUG] Task is available.
[0][DEBUG] Switching task from 9 to 4 (stack 0x7511F60 => 0x70BDDD0)
[0][DEBUG] Switching FPU owner from task 9 to 4
[0][DEBUG] Deallocating stacks at 0x7500000 with a size of 1088 KB
[3][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Deallocate TLS at 0x7614000 (size 0x1000)
[1][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Task 4 is waiting for task 9
[0][DEBUG] Blocking task 4
[0][DEBUG] Cleaning up task 9
[0][DEBUG] Waking up task 4 on core 0
[0][DEBUG] Task is available.
Pi: 3.1415926535897665 (with 2 threads)
Test pi_parallel ... ok
[0][DEBUG] Creating new task 10
[0][DEBUG] Create stacks at 0x7500000 with a size of 1088 KB
[1][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Set up TLS at 0x7614120, tdata_size 0x0, tls_size 0x108
[2][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Creating task 10 with priority 2 on core 1
[1][DEBUG] Received Wakeup Interrupt
[1][DEBUG] Task is available.
[1][DEBUG] Switching task from 1 to 10 (stack 0x703BD50 => 0x7511F60)
[0][DEBUG] Creating new task 11
[1][DEBUG] Switching FPU owner from task 6 to 10
[0][DEBUG] Create stacks at 0x7615000 with a size of 1088 KB
[1][DEBUG] Deallocating stacks at 0x71C1000 with a size of 1088 KB
[3][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Deallocate TLS at 0x72d5000 (size 0x1000)
[0][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] sys_notify: invalid address to condition variable
[1][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Set up TLS at 0x71c1120, tdata_size 0x0, tls_size 0x108
[3][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Creating task 11 with priority 2 on core 2
[2][DEBUG] Received Wakeup Interrupt
[0][DEBUG] Creating new task 12
[2][DEBUG] Task is available.
[0][DEBUG] Create stacks at 0x71C2000 with a size of 1088 KB
[2][DEBUG] Switching task from 2 to 11 (stack 0x7063D50 => 0x7626F60)
[1][DEBUG] Create condition variable queue
[3][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Blocking task 10
[2][DEBUG] Switching FPU owner from task 7 to 11
[2][DEBUG] Deallocating stacks at 0x72D6000 with a size of 1088 KB
[1][DEBUG] Only Idle Task is available.
[1][DEBUG] Switching task from 10 to 1 (stack 0x7511F60 => 0x703BD50)
[0][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Deallocate TLS at 0x73ea000 (size 0x1000)
[1][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] sys_notify: invalid address to condition variable
[2][DEBUG] Blocking task 11
[2][DEBUG] Only Idle Task is available.
[2][DEBUG] Switching task from 11 to 2 (stack 0x7626F60 => 0x7063D50)
[0][DEBUG] Set up TLS at 0x72d6120, tdata_size 0x0, tls_size 0x108
[1][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Creating task 12 with priority 2 on core 3
[3][DEBUG] Received Wakeup Interrupt
[3][DEBUG] Task is available.
[0][DEBUG] Creating new task 13
[3][DEBUG] Switching task from 3 to 12 (stack 0x708BD50 => 0x71D3F60)
[0][DEBUG] Create stacks at 0x72D7000 with a size of 1088 KB
[3][DEBUG] Switching FPU owner from task 8 to 12
[1][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Deallocating stacks at 0x73EB000 with a size of 1088 KB
[1][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Deallocate TLS at 0x74ff000 (size 0x1000)
[0][DEBUG] Received TLB Flush Interrupt
[2][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] sys_notify: invalid address to condition variable
[3][DEBUG] Blocking task 12
[3][DEBUG] Only Idle Task is available.
[3][DEBUG] Switching task from 12 to 3 (stack 0x71D3F60 => 0x708BD50)
[0][DEBUG] Set up TLS at 0x73eb120, tdata_size 0x0, tls_size 0x108
[2][DEBUG] Received TLB Flush Interrupt
[1][DEBUG] Received TLB Flush Interrupt
[3][DEBUG] Received TLB Flush Interrupt
[0][DEBUG] Creating task 13 with priority 2 on core 0
[2][DEBUG] Received Wakeup Interrupt
[1][DEBUG] Received Wakeup Interrupt
[3][DEBUG] Received Wakeup Interrupt
[0][DEBUG] Create condition variable queue
[0][DEBUG] Blocking task 4
[0][DEBUG] Task is available.
[0][DEBUG] Switching task from 4 to 13 (stack 0x70BDDD0 => 0x72E8F60)
[3][DEBUG] Waking up task 12 on core 3
[2][DEBUG] Waking up task 11 on core 2
[1][DEBUG] Waking up task 10 on core 1
[0][DEBUG] Switching FPU owner from task 4 to 13
[2][DEBUG] Task is available.
[1][DEBUG] Task is available.
[2][DEBUG] Switching task from 2 to 11 (stack 0x7063D50 => 0x7626E40)
[0][DEBUG] sys_notify: invalid address to condition variable
[1][DEBUG] Switching task from 1 to 10 (stack 0x703BD50 => 0x7511E40)
[3][DEBUG] Task is available.
[3][DEBUG] Switching task from 3 to 12 (stack 0x708BD50 => 0x71D3E40)
[1][DEBUG] Blocking task 10
[1][DEBUG] Only Idle Task is available.
[1][DEBUG] Switching task from 10 to 1 (stack 0x7511E40 => 0x703BD50)
[1][DEBUG] Received Wakeup Interrupt
[1][DEBUG] Waking up task 10 on core 1
[1][DEBUG] Task is available.
[1][DEBUG] Switching task from 1 to 10 (stack 0x703BD50 => 0x7511DA0)
[0][DEBUG] Waking up task 4 on core 0
[0][DEBUG] Time slice expired for current task.
[0][DEBUG] Switching task from 13 to 4 (stack 0x72E8F60 => 0x70BDE40)
[0][DEBUG] Switching FPU owner from task 13 to 4
[2][DEBUG] Blocking task 11
[2][DEBUG] Only Idle Task is available.
[0][DEBUG] Blocking task 4
[2][DEBUG] Switching task from 11 to 2 (stack 0x7626E40 => 0x7063D50)
[0][DEBUG] Task is available.
[2][DEBUG] Received Wakeup Interrupt
[0][DEBUG] Switching task from 4 to 13 (stack 0x70BDE40 => 0x72E8E40)
[2][DEBUG] Waking up task 11 on core 2
[0][DEBUG] Switching FPU owner from task 4 to 13
[2][DEBUG] Task is available.
[2][DEBUG] Switching task from 2 to 11 (stack 0x7063D50 => 0x7626E40)
[0][DEBUG] Received Wakeup Interrupt
[0][DEBUG] Waking up task 4 on core 0
[2][DEBUG] Blocking task 11
[2][DEBUG] Only Idle Task is available.
[2][DEBUG] Switching task from 11 to 2 (stack 0x7626E40 => 0x7063D50)
[3][DEBUG] Blocking task 12
[3][DEBUG] Only Idle Task is available.
[3][DEBUG] Switching task from 12 to 3 (stack 0x71D3E40 => 0x708BD50)
[1][DEBUG] Blocking task 10
[1][DEBUG] Only Idle Task is available.
[1][DEBUG] Switching task from 10 to 1 (stack 0x7511DA0 => 0x703BD50)
[0][DEBUG] Blocking task 13
[0][DEBUG] Task is available.
[0][DEBUG] Switching task from 13 to 4 (stack 0x72E8E40 => 0x70BDE40)
[0][DEBUG] Switching FPU owner from task 13 to 4
[1][DEBUG] Received Wakeup Interrupt
[3][DEBUG] Received Wakeup Interrupt
[2][DEBUG] Received Wakeup Interrupt
[0][DEBUG] Waking up task 13 on core 0
[1][DEBUG] Waking up task 10 on core 1
[3][DEBUG] Waking up task 12 on core 3
[2][DEBUG] Waking up task 11 on core 2
[0][DEBUG] Blocking task 4
[1][DEBUG] Task is available.
[3][DEBUG] Task is available.
[0][DEBUG] Task is available.
[1][DEBUG] Switching task from 1 to 10 (stack 0x703BD50 => 0x7511E40)
[3][DEBUG] Switching task from 3 to 12 (stack 0x708BD50 => 0x71D3E40)
[2][DEBUG] Task is available.
[0][DEBUG] Switching task from 4 to 13 (stack 0x70BDE40 => 0x72E8E40)
[2][DEBUG] Switching task from 2 to 11 (stack 0x7063D50 => 0x7626E40)
[0][DEBUG] Switching FPU owner from task 4 to 13
[2][DEBUG] Blocking task 11
[2][DEBUG] Only Idle Task is available.
[2][DEBUG] Switching task from 11 to 2 (stack 0x7626E40 => 0x7063D50)
[0][DEBUG] Blocking task 13
[0][DEBUG] Received Wakeup Interrupt
[0][DEBUG] Waking up task 4 on core 0
[0][DEBUG] Task is available.
[0][DEBUG] Switching task from 13 to 4 (stack 0x72E8E40 => 0x70BDE40)
[3][DEBUG] Blocking task 12
[0][DEBUG] Switching FPU owner from task 13 to 4
[3][DEBUG] Only Idle Task is available.
[2][DEBUG] Received Wakeup Interrupt
[3][DEBUG] Switching task from 12 to 3 (stack 0x71D3E40 => 0x708BD50)
[0][DEBUG] Blocking task 4
[2][DEBUG] Waking up task 11 on core 2
[3][DEBUG] Received Wakeup Interrupt
[0][DEBUG] Only Idle Task is available.
[2][DEBUG] Task is available.
[3][DEBUG] Waking up task 12 on core 3
[0][DEBUG] Switching task from 4 to 0 (stack 0x70BDE40 => 0x1FFDD0)
[2][DEBUG] Switching task from 2 to 11 (stack 0x7063D50 => 0x7626E40)
[3][DEBUG] Task is available.
[3][DEBUG] Switching task from 3 to 12 (stack 0x708BD50 => 0x71D3E40)
[0][DEBUG] Received Wakeup Interrupt
[3][DEBUG] Blocking task 12
[3][DEBUG] Only Idle Task is available.
[3][DEBUG] Switching task from 12 to 3 (stack 0x71D3E40 => 0x708BD50)
[2][DEBUG] Blocking task 11
[2][DEBUG] Only Idle Task is available.
[2][DEBUG] Switching task from 11 to 2 (stack 0x7626E40 => 0x7063D50)
[1][DEBUG] Blocking task 10
[1][DEBUG] Only Idle Task is available.
[1][DEBUG] Switching task from 10 to 1 (stack 0x7511E40 => 0x703BD50)