From 093eafd39ae4ff0061e9f637f348b268a8db3b46 Mon Sep 17 00:00:00 2001
From: highway900 <1100256+highway900@users.noreply.github.com>
Date: Thu, 17 Feb 2022 14:42:10 +1100
Subject: [PATCH] Update README.md

The url for yosys was incorrect or out dated, resolves to a domain parking service. Include github repo url.
---
 README.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index c07e144..6ee1eac 100644
--- a/README.md
+++ b/README.md
@@ -34,7 +34,8 @@ License: MIT
 ### Yosys
 Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
 
-Homepage: http://www.clifford.at/yosys/
+Homepage: https://yosyshq.net/yosys/
+Github repository: https://github.com/YosysHQ/yosys
 
 License: ISC