{"payload":{"header_redesign_enabled":false,"results":[{"id":"402382868","archived":false,"color":"#B9D9FF","followers":9,"has_funding_file":false,"hl_name":"hiiask/mdw21","hl_trunc_description":"Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis","language":"AGS Script","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":402382868,"name":"mdw21","owner_id":60669669,"owner_login":"hiiask","updated_at":"2022-12-09T07:50:27.356Z","has_issues":true}},"sponsorable":false,"topics":["memory","ieee","analog-design","circuit-design","sram-cell","memory-design","sram-memories"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":50,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Ahiiask%252Fmdw21%2B%2Blanguage%253A%2522AGS%2BScript%2522","metadata":null,"csrf_tokens":{"/hiiask/mdw21/star":{"post":"4ThjmMSMl9xZ5OAi3_npptibqM3Ek3Jup_DtOcVarhw8BiPBRZVwiwcwTcJ8puMjKQsqeIKZ4Yhoa3-sjcS4Aw"},"/hiiask/mdw21/unstar":{"post":"QrSP2Lhn5ivALWbd2e4xQo0Lv6aGnkhrNKPAmjoMO5uNLk9xvIQkdpbA_Rsq_ImLtbZU1DeqpsLIx1St0aG78Q"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"6qvot9llYPM9hpL6y5vCTUcNsJJaD7JLVs738ZHS3sxF8HGseDFht_evT1yhhPsDFVSMNEJjSiTcwctamHB8mw"}}},"title":"Repository search results"}