This Project is about design and simulation of PWM generator with variable duty cycle.
By dividing an electrical signal into discrete pieces, pulse-width modulation (PWM) or pulse-duration modulation (PDM) is a technique for lowering the average power produced by an electrical signal. By rapidly flipping the switch between the supply and the load on and off, the average amount of voltage (and current) provided to the load is managed. The total power provided to the load increases while the switch is on for a longer period of time compared to when it is off. Depending on the load and application, the power supply's switching rate (or frequency) might change significantly.
A low duty cycle equates to low power because the electricity is off for the most of the time; the word duty cycle reflects the ratio of "on" time to the regular interval or "period" of time. Duty cycle is measured in percentages, with 100 percent representing total on. A digital signal has a duty cycle of 50% and looks like a "square" wave when it is on for 50% of the time and off for the other 50%. A digital signal has a duty cycle of >50% when it spends more time in the on state than the off state. A digital signal has a duty cycle of 50% when it spends 50% more time in the off state than the on state.
Duty cycle = Ton/T
- Servos
- Telecommunications
- Power Delievery
- Voltage regulation
- Audio effects and amplification
- Soft blinking LED indicator
This PWM generator generates 10Mhz signal. We can control duty cycles in steps of 10%. The default duty cycle is 50%. Along with clock signal we provide another two external signals to increase and decrease the duty cycle.
The key components we need for this particular circuit are an n-bit counter and comparator. The duty passed to the comparator is compared to the counter's current value. If the counter's current value is less than the required value, the comparator produces a high output. Similar to this, if the counter's current value is higher than its duty, the comparator's output will be low. Since the counter starts at zero, the comparator initially produces a large output, which decreases as the counter approaches its duty. Therefore, we can manage duty cycle by managing duty.
Since the counter is sequential and the comparator is a combinational circuit, there may be an intermediate state like 111 that is higher or lower than duty when counting from 011 to 100 as a result of inappropriate delays. A glitch might result from this. The output of the comparator is routed through a D flipflop in order to prevent these errors.
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format.
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
open terminal and type following commands- sudo apt-get update from terminal.
- sudo apt-get install iverilog.
- sudo apt-get install gtkwave.
Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.
Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). More information and documentation can be found on the Yosys web site:
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To install yosys, You can follow this link https://github.com/YosysHQ/yosys
$ yosys
$ yosys> script yosys_run.sh
After running
stat
it gives stat as shown below:
By running the test bench with the netlist file produced by the synthesis as the design under test, GLS generates the simulation results. Since Netlist and RTL code are logically equivalent, the same test bench can be utilised. This is done to check the design's logical accuracy once it has been synthesised. Making sure the design's timing is satisfied.
Folllowing are the commands to run the GLS simulation:
iverilog -DFUNCTIONAL -DUNIT_DELAY=#1 primitives.v sky130_fd_sc_hd.v iiitb_pwm_gen_synth.v iiitb_pwm_gen_tb.v
./a.out
gtkwave pwm.vcd
I have primitives.v and sky123_fd_sc_hd.v in same folder with design files, if not so than kindly provide whole path in the 1st line of commands above.
The output waveform for the RTL design file should match the gtkwave output for the netlist. We can use the same testbench and compare the waveforms because the netlist and design code have the same set of inputs and outputs.
We can observe that output of functional simulation is matching with the output of gate level simulation, this means that the netlist generated by yosys is correct.
Place and Route (PnR), the central component of any ASIC implementation, is carried out by a number of important open source tools that are integrated into Openlane flow. The phases and associated tools that Openlane calls for the above-described features are listed below:
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- Synthesizing the clock tree (TritonCTS).
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- Performing global routing to generate a guide file for the detailed router (FastRoute).
- Performing detailed routing (TritonRoute)
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- Streaming out the final GDSII layout file from the routed def (Magic).
OpenLANE is an opensource tool or flow used for opensource tape-outs. The OpenLANE flow comprises a variety of tools such as Yosys, ABC, OpenSTA, Fault, OpenROAD app, Netgen and Magic which are used to harden chips and macros, i.e. generate final GDSII from the design RTL. The primary goal of OpenLANE is to produce clean GDSII with no human intervention. OpenLANE has been tuned to function for the Google-Skywater130 Opensource Process Design Kit.
More about Openlane at : https://github.com/The-OpenROAD-Project/OpenLane
apt install -y build-essential python3 python3-venv python3-pip
$ sudo apt-get remove docker docker-engine docker.io containerd runc (removes older version of docker if installed)
$ sudo apt-get update
$ sudo apt-get install \
ca-certificates \
curl \
gnupg \
lsb-release
$ sudo mkdir -p /etc/apt/keyrings
$ curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo gpg --dearmor -o /etc/apt/keyrings/docker.gpg
$ echo \
"deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.gpg] https://download.docker.com/linux/ubuntu \
$(lsb_release -cs) stable" | sudo tee /etc/apt/sources.list.d/docker.list > /dev/null
$ sudo apt-get update
$ sudo apt-get install docker-ce docker-ce-cli containerd.io docker-compose-plugin
$ apt-cache madison docker-ce (copy the version string you want to install)
$ sudo apt-get install docker-ce=<VERSION_STRING> docker-ce-cli=<VERSION_STRING> containerd.io docker-compose-plugin (paste the version string copies in place of <VERSION_STRING>)
$ sudo docker run hello-world (If the docker is successfully installed u will get a success message here)
for more about docker installation you can check the following link: https://docs.docker.com/engine/install/ubuntu/ After installing Docker we are ready for OpenLane installation.
first go to home directory->
$ git clone https://github.com/The-OpenROAD-Project/OpenLane.git
$ cd OpenLane/
$ make
$ make test
If it ended with saying Basic test passed then open lane installed succesfully.
The venerable VLSI layout tool Magic was created in the 1980s at Berkeley by John Ousterhout, who is now best known for creating the scripting language Tcl. Magic has maintained its popularity among colleges and small businesses in great part because of its permissive Berkeley open-source licence. The open-source licence has made it possible for VLSI experts with a programming inclination to put innovative ideas into practise and support magic's further advancement in fabrication technology. The well-designed basic algorithms, however, are what give magic the most of its notoriety. Even those who finally rely on commercial tools for their product design flow frequently identify magic as the most user-friendly tool for circuit layout. You can find More about Magic at: http://opencircuitdesign.com/magic/index.html
Before installation Magic install the following softwares first:
$ sudo apt-get install m4
$ sudo apt-get install tcsh
$ sudo apt-get install csh
$ sudo apt-get install libx11-dev
$ sudo apt-get install tcl-dev tk-dev
$ sudo apt-get install libcairo2-dev
$ sudo apt-get install mesa-common-dev libglu1-mesa-dev
$ sudo apt-get install libncurses-dev
After running all the above commands we will finally proceed for magic installation.
First go to home directory and open terminal and write the following commands->
$ git clone https://github.com/RTimothyEdwards/magic
$ cd magic/
$ ./configure
$ sudo make
$ sudo make install
After installation type magic in terminal a magic window will pop up, which means magic is installed properly.
KLayout is a GDS and OASIS file viewer.KLayout is published under GNU public license GPL version 2 or any later version (www.gnu.org) in compliance with the requirements for using the Qt open source licence.
$ sudo apt-get install klayout
To open just type Klayout in terminal, a window will appear as shown below.
ngspice is the open source spice simulator for electric and electronic circuits. ngspice offers a wealth of device models for active, passive, analog, and digital elements. Model parameters are provided by our collections, by the semiconductor device manufacturers, or from semiconductor foundries. The user adds her circuits as a netlist, and the output is one or more graphs of currents, voltages and other electrical quantities or is saved in a data file. It does not provide schematic entry. Its input is command line or file based. There are however third party interfaces available.
$ sudo apt-get install ngspice
open the openlane folder in terminal, and run the following commands:
$ git clone https://github.com/nickson-jose/vsdstdcelldesign.git
$ cd vsdstdcelldesign
$ cp ./libs/sky130A.tech sky130A.tech
$ magic -
T sky130A.tech sky130_inv.mag &
In Sky130 the first layer is called the local interconnect layer or Locali.
To verify whether the layout is that of CMOS inverter, verification of P-diffusiona nd N-diffusion regions with Polysilicon can be observed.
Other verification steps are to check drain and source connections. The drains of both PMOS and NMOS must be connected to output port (here, Y) and the sources of both must be connected to power supply VDD (here, VPWR). LEF or library exchange format: A format that tells us about cell boundaries, VDD and GND lines. It contains no info about the logic of circuit and is also used to protect the IP. SPICE extraction: Within the Magic environment, following commands are used in tkcon to achieve .mag to .spice extraction:
extract all
ext2spice cthresh 0 rethresh 0
ext2spice
This generates the sky130_in.spice file. This SPICE deck is edited to include pshort.lib and nshort.lib which are the PMOS and NMOS libraries respectively. In addition, the minimum grid size of inverter is measured from the magic layout and incorporated into the deck as: .option scale=0.01u. The model names in the MOSFET definitions are changed to pshort.model.0 and nshort.model.0 respectively for PMOS and NMOS.
Finally voltage sources and simulation commands are defined as follows:
VDD VPWR 0 3.3V
VSS VGND 0 0
Va A VGND PUSLE(0V 3.3V 0 0.1ns 0.1 ns 2ns 4ns)
.tran 1n 20n
.control
run
.endc
.end
The final sky130_inv.spice file is modified to:
For simulation, ngspice is invoked in the terminal:
ngspice sky130_inv.spice
The output "y" is to be plotted with "time" and swept over the input "a":
plot y vs time a
The waveform obtained is shown below:
Four timing parameters are used to characterize the inverter standard cell:
- Rise transition: Time taken for the output to rise from 20% of max value to 80% of max value
- Fall transition- Time taken for the output to fall from 80% of max value to 20% of max value
- Cell rise delay = time(50% output rise) - time(50% input fall)
- Cell fall delay = time(50% output fall) - time(50% input rise)
The above timing parameters can be computed by noting down various values from the ngspice waveform.
Rise transition = (2.23843 - 2.17935) = 59.08ps
Fall transition = (4.09291 - 4.05004) = 42.87ps
Cell rise delay = (2.20636 - 2.15) = 56.36ps
Cell fall delay = (4.07479 - 4.05) = 24.79ps
$ magic -T sky130A.tech sky130_vsdinv.mag
In Magic Layout window, first source the .mag file for the design (here inverter). Then Edit >> Text which opens up a dialogue box.
Before the CMOS Inverter standard cell LEF is extracted, the purpose of ports must be defined:
Select port A in magic:
port class input
port use signal
Select Y area
port class output
port class signal
Select VPWR area
port class inout
port use power
Select VGND area
port class inout
port use ground
LEF extraction can be carried out in tkcon as follows:
lef write
The layout is generated using OpenLane. To run a custom design on openlane, Navigate to the openlane folder and run the following commands:
$ cd designs
$ mkdir iiitb_pwm_gen
$ cd iiitb_pwm_gen
$ mkdir src
$ touch config.json
$ cd src
$ touch iiitb_pwm_gen.v
Copy sky130_fd_sc_hd__fast.lib, sky130_fd_sc_hd__slow.lib, sky130_fd_sc_hd__typical.liband sky130_vsdinv.lef files to src folder in your design.
The contents of src file is shown below:
The contents of json file should be modified as:
Save all the changes made above and Navigate to the openlane folder in terminal and give the following command :
$ sudo make mount
$ ./flow.tcl -interactive
A tcl console will be opened, now we will give following commands:
% package require openlane 0.9
% prep -design iiitb_pwm_gen
The following commands are to merge external the lef files to the merged.nom.lef. In our case sky130_vsdiat is getting merged to the lef file
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
The contents of the merged.nom.lef file should contain the Macro definition of sky130_vsdinv
% run_synthesis
- Calcuation of Flop Ratio:
Flop ratio = Number of D Flip flops
______________________
Total Number of cells
The flop ratio of my design is 0.21229
The sky130_vsdinv should also reflect in your netlist after synthesis
Timing contraints of design:
In the VLSI physical design, floorplanning is an essential design step, as it determines the size, shape, and locations of modules in a chip and as such it estimates the total chip area, the interconnects, and, delay.
% run_floorplan
- Die Area
- Core area
Post the floorplan run, a .def file will have been created within the results/floorplan directory. We may review floorplan files by checking the floorplan.tcl. The system defaults will have been overriden by switches set in conifg.tcl and further overriden by switches set in sky130A_sky130_fd_sc_hd_config.tcl.
For floorplan view navigate to /home/himanshu/OpenLane/designs/iiitb_pwm_gen/runs/RUN_2022.08.30_14.11.34/results/floorplan and then type the following magic command :
magic -T /home/himanshu/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read lef ../../tmp/merged.nom.lef def read iiitb_pwm_gen.def &
Floorplan View
Placement is the process of placing the standard cells inside the core boundary in an optimal location. The tool tries to place the standard cell in such a way that the design should have minimal congestions and the best timing.
% run_placement
Navigate to /home/himanshu/OpenLane/designs/iiitb_pwm_gen/runs/RUN_2022.08.30_14.11.34/results/placement and type magic command:
magic -T /home/himanshu/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read lef ../../tmp/merged.nom.lef def read iiitb_pwm_gen.def &
Placement View
sky130_vsdinv placement view
Clock Tree Synthesis is a technique for distributing the clock equally among all sequential parts of a VLSI design. The purpose of Clock Tree Synthesis is to reduce skew and delay. Clock Tree Synthesis is provided the placement data as well as the clock tree limitations as input.
% run_cts
Making physical connections between signal pins using metal layers are called Routing. Routing is the stage after CTS and optimization where exact paths for the interconnection of standard cells and macros and I/O pins are determined.
% run_routing
Navigate to /home/himanshu/OpenLane/designs/iiitb_pwm_gen/runs/RUN_2022.08.30_14.11.34/results/placement and type magic command:
magic -T /home/himanshu/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read lef ../../tmp/merged.nom.lef def read iiitb_pwm_gen.def &
Routing View
sky130_vsdinv routing view
Area Report
Here we are generating the layout in the non-interactive mode or the automatic mode. In this we cant interact with the flow in the middle of each stage of the flow.The flow completes all the stages starting from synthesis until you obtain the final layout and the reports of various stages which specify the violations and problems if present during the flow.
$ cd designs
$ mkdir iiitb_pwm_gen
$ cd iiitb_pwm_gen
$ mkdir src
$ touch config.json
$ cd src
$ touch iiitb_pwm_gen.v
Copy sky130_fd_sc_hd__fast.lib, sky130_fd_sc_hd__slow.lib, sky130_fd_sc_hd__typical.liband sky130_vsdinv.lef files to src folder in your design.
The contents of src file is shown below:
The contents of json file should be modified as:
Save all the changes made above and Navigate to the openlane folder in terminal and give the following command :
sudo make mount
./flow.tcl -design iiitb_pwm_gen
All the steps will be automated and all the files will be generated.
After running all the steps flow complete message will apperas shown below.
After the flow complete message open terminal and write following commands to view layout in klayout:
cd /home/himanshu/OpenLane/designs/iiitb_pwm_gen/runs/RUN_2022.08.31_17.08.00/results/signoff
klayout iiitb_pwm_gen.mag
Layout View
Gate count = 179
Area = 11773.920 um^2
performance = 1/(clock period-slack = 1/(10-6.63)ps =296.74GHz)
Flop ratio = 40/179 = 0.2234
- Himanshu Kumar Rai
- Kunal Ghosh
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
- Himanshu Kumar Rai, MS, International Institute of Information Technology, Bangalore himanshukumar.rai@iiitb.ac.in
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com