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Fix bug where process was resumed multiple times

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1 parent dbb735c commit 7047e2759e1e8336a990217adf2d212b5d0e2d83 @nickg nickg committed Apr 11, 2012
Showing with 34 additions and 3 deletions.
  1. +3 −3 src/rt/rtkern.c
  2. +4 −0 test/regress/gold/wait6.txt
  3. +1 −0 test/regress/testlist.txt
  4. +26 −0 test/regress/wait6.vhd
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6 src/rt/rtkern.c
@@ -271,14 +271,14 @@ void _sched_event(void *_sig, int32_t n)
if (it == NULL) {
struct sens_list *node = rt_alloc(sens_list_stack);
node->proc = active_proc;
- node->wakeup_gen = active_proc->wakeup_gen + 1;
+ node->wakeup_gen = active_proc->wakeup_gen;
node->next = sig[i].sensitive;
sig[i].sensitive = node;
}
else {
// Reuse the stale entry
- it->wakeup_gen = active_proc->wakeup_gen + 1;
+ it->wakeup_gen = active_proc->wakeup_gen;
}
}
}
@@ -628,7 +628,6 @@ static void rt_run(struct rt_proc *proc, bool reset)
active_proc = proc;
(*proc->proc_fn)(reset ? 1 : 0);
- ++(proc->wakeup_gen);
// Free any temporary memory allocated by the process
while (proc->tmp_chunks) {
@@ -660,6 +659,7 @@ static void rt_wakeup(struct sens_list *sl)
if (sl->wakeup_gen == sl->proc->wakeup_gen) {
TRACE("wakeup process %s", istr(tree_ident(sl->proc->source)));
+ ++(sl->proc->wakeup_gen);
sl->next = resume;
resume = sl;
}
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4 test/regress/gold/wait6.txt
@@ -0,0 +1,4 @@
+0ms+0: Report Note: x changed '0' '0' '0' '0'
+0ms+1: Report Note: x changed '0' '0' '0' '1'
+1ns+1: Report Note: x changed '0' '0' '1' '0'
+2ns+1: Report Note: x changed '1' '1' '1' '1'
View
1 test/regress/testlist.txt
@@ -65,3 +65,4 @@ elab3 normal,gold
func6 normal
case2 normal
case3 normal
+wait6 normal,gold
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26 test/regress/wait6.vhd
@@ -0,0 +1,26 @@
+entity wait6 is
+end entity;
+
+architecture test of wait6 is
+ signal x : bit_vector(3 downto 0);
+begin
+
+ print: process (x) is
+ begin
+ report "x changed " & bit'image(x(3)) & " "
+ & bit'image(x(2)) & " "
+ & bit'image(x(1)) & " "
+ & bit'image(x(0));
+ end process;
+
+ stim: process is
+ begin
+ x <= X"1";
+ wait for 1 ns;
+ x <= X"2";
+ wait for 1 ns;
+ x <= X"f";
+ wait;
+ end process;
+
+end architecture;

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