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arm64jit: Enable safe memory for lwl/lwr.

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unknownbrackets committed Dec 30, 2017
1 parent c00044c commit 0fc8274ec4e084297aba95c38f106320888df78c
Showing with 6 additions and 6 deletions.
  1. +6 −6 Core/MIPS/ARM64/Arm64CompLoadStore.cpp
@@ -176,18 +176,18 @@ namespace MIPSComp {
} else {
gpr.MapInIn(rt, rs);
}
gpr.SpillLock(rt);
gpr.SpillLock(rs);
// Need to get temps before skipping safe mem.
ARM64Reg LR_SCRATCH3 = gpr.GetAndLockTempR();
ARM64Reg LR_SCRATCH4 = gpr.GetAndLockTempR();
if (false && !g_Config.bFastMemory && rs != MIPS_REG_SP) {
if (!g_Config.bFastMemory && rs != MIPS_REG_SP) {
skips = SetScratch1ForSafeAddress(rs, offset, SCRATCH2);
} else {
SetScratch1ToEffectiveAddress(rs, offset);
}
// We can lose rs now, since we have it in SCRATCH1.
gpr.SpillLock(rt);
ARM64Reg LR_SCRATCH3 = gpr.GetAndLockTempR();
ARM64Reg LR_SCRATCH4 = gpr.GetAndLockTempR();
// Here's our shift amount.
ANDI2R(SCRATCH2, SCRATCH1, 3);
LSL(SCRATCH2, SCRATCH2, 3);

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