diff --git a/Core/MIPS/x86/CompLoadStore.cpp b/Core/MIPS/x86/CompLoadStore.cpp
index 64d6c1773d0b..1cc4240a3099 100644
--- a/Core/MIPS/x86/CompLoadStore.cpp
+++ b/Core/MIPS/x86/CompLoadStore.cpp
@@ -80,7 +80,7 @@ namespace MIPSComp {
 		return in;
 	}
 
-	void Jit::CompITypeMemWrite(MIPSOpcode op, u32 bits, const void *safeFunc)
+	void Jit::CompITypeMemWrite(MIPSOpcode op, u32 bits, const void *safeFunc, bool makeRTWritable)
 	{
 		CONDITIONAL_DISABLE(LSU);
 		int offset = _IMM16;
@@ -90,6 +90,9 @@ namespace MIPSComp {
 		gpr.Lock(rt, rs);
 		
 		if (rt == MIPS_REG_ZERO || gpr.R(rt).IsImm()) {
+			if (makeRTWritable) {
+				gpr.MapReg(rt, true, true);
+			}
 			// NOTICE_LOG(JIT, "%d-bit Imm at %08x : %08x", bits, js.blockStart, (u32)gpr.R(rt).GetImmValue());
 		} else {
 			gpr.MapReg(rt, true, false);
@@ -428,8 +431,7 @@ namespace MIPSComp {
 			CMP(8, MDisp(X64JitConstants::CTXREG, -128 + offsetof(MIPSState, llBit)), Imm8(1));
 			skipStore = J_CC(CC_NE);
 
-			CompITypeMemWrite(op, 32, safeMemFuncs.writeU32);
-			gpr.MapReg(rt, true, true);
+			CompITypeMemWrite(op, 32, safeMemFuncs.writeU32, true);
 			MOV(32, gpr.R(rt), Imm32(1));
 			finish = J();
 
diff --git a/Core/MIPS/x86/Jit.h b/Core/MIPS/x86/Jit.h
index 0a56cfae5b32..423678500664 100644
--- a/Core/MIPS/x86/Jit.h
+++ b/Core/MIPS/x86/Jit.h
@@ -225,7 +225,7 @@ class Jit : public Gen::XCodeBlock, public JitInterface, public MIPSFrontendInte
 	void CompITypeMemRead(MIPSOpcode op, u32 bits, void (XEmitter::*mov)(int, int, Gen::X64Reg, Gen::OpArg), T (*safeFunc)(u32 addr)) {
 		CompITypeMemRead(op, bits, mov, (const void *)safeFunc);
 	}
-	void CompITypeMemWrite(MIPSOpcode op, u32 bits, const void *safeFunc);
+	void CompITypeMemWrite(MIPSOpcode op, u32 bits, const void *safeFunc, bool makeRTWritable = false);
 	template <typename T>
 	void CompITypeMemWrite(MIPSOpcode op, u32 bits, void (*safeFunc)(T val, u32 addr)) {
 		CompITypeMemWrite(op, bits, (const void *)safeFunc);