From 2419e5680a94b9b6f46dd00e808011ed962b2cef Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Fri, 18 Nov 2022 17:53:53 -0800
Subject: [PATCH] irjit: Correct VV2Op SIMD check.

It's unlikely, but possible, uninitialized data could cause
IsConsecutive4() to return true when n < 4.
---
 Core/MIPS/IR/IRCompVFPU.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Core/MIPS/IR/IRCompVFPU.cpp b/Core/MIPS/IR/IRCompVFPU.cpp
index 74b0615547b5..8515b6031f87 100644
--- a/Core/MIPS/IR/IRCompVFPU.cpp
+++ b/Core/MIPS/IR/IRCompVFPU.cpp
@@ -788,7 +788,7 @@ namespace MIPSComp {
 		VectorSize sz = GetVecSize(op);
 		int n = GetNumVectorElements(sz);
 
-		u8 sregs[4], dregs[4];
+		u8 sregs[4]{}, dregs[4]{};
 		GetVectorRegsPrefixS(sregs, sz, vs);
 		GetVectorRegsPrefixD(dregs, sz, vd);
 
@@ -809,7 +809,8 @@ namespace MIPSComp {
 		case 0:  // vmov
 		case 1:  // vabs
 		case 2:  // vneg
-			canSIMD = true;
+			// Our Vec4 ops require aligned regs and sets of 4.
+			canSIMD = n == 4 && (sregs[0] & 3) == 0 && (dregs[0] & 3) == 0;
 			break;
 		}