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IR: This optimization is safe when all three regs are consecutive, so…

… avoid disabling it unnecessarily.
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hrydgard committed Jan 10, 2018
1 parent fb0e814 commit 34f79904fd71e2c45028dcf70cc64bd4d75744c7
Showing with 2 additions and 3 deletions.
  1. +2 −3 Core/MIPS/IR/IRCompVFPU.cpp
@@ -617,17 +617,16 @@ namespace MIPSComp {
GetVectorRegsPrefixD(dregs, sz, _VD);
u8 tempregs[4];
bool usingTemps = false;
for (int i = 0; i < n; i++) {
if (!IsOverlapSafe(dregs[i], n, sregs, n, tregs)) {
tempregs[i] = IRVTEMP_0 + i;
usingTemps = true;
} else {
tempregs[i] = dregs[i];
}
}
if (allowSIMD && sz == V_Quad && !usingTemps && IsConsecutive4(dregs) && IsConsecutive4(sregs) && IsConsecutive4(tregs)) {
// If all three are consecutive 4, we're safe regardless of if we use temps so we should not check that here.
if (allowSIMD && sz == V_Quad && IsConsecutive4(dregs) && IsConsecutive4(sregs) && IsConsecutive4(tregs)) {
IROp opFunc = IROp::Nop;
switch (op >> 26) {
case 24: //VFPU0

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