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arm64jit: Remove unnecessary address masking.

We use views like on x86_64, so this isn't needed.
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unknownbrackets committed Dec 29, 2017
1 parent 27116dc commit 5177db0f9188ca4540d215f317401d6e8c1b7d03
@@ -102,7 +102,7 @@ void Arm64Jit::Comp_FPULS(MIPSOpcode op)
fpr.SpillLock(ft);
fpr.MapReg(ft, MAP_NOINIT | MAP_DIRTY);
if (gpr.IsImm(rs)) {
u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
u32 addr = offset + gpr.GetImm(rs);
gpr.SetRegImm(SCRATCH1, addr);
} else {
gpr.MapReg(rs);
@@ -129,7 +129,7 @@ void Arm64Jit::Comp_FPULS(MIPSOpcode op)
fpr.MapReg(ft);
if (gpr.IsImm(rs)) {
u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
u32 addr = offset + gpr.GetImm(rs);
gpr.SetRegImm(SCRATCH1, addr);
} else {
gpr.MapReg(rs);
@@ -133,13 +133,12 @@ namespace MIPSComp {
std::vector<FixupBranch> skips;
if (gpr.IsImm(rs) && Memory::IsValidAddress(iaddr)) {
u32 addr = iaddr & 0x3FFFFFFF;
// Need to initialize since this only loads part of the register.
// But rs no longer matters (even if rs == rt) since we have the address.
gpr.MapReg(rt, load ? MAP_DIRTY : 0);
gpr.SetRegImm(SCRATCH1, addr & ~3);
gpr.SetRegImm(SCRATCH1, iaddr & ~3);
u8 shift = (addr & 3) * 8;
u8 shift = (iaddr & 3) * 8;
switch (o) {
case 34: // lwl
@@ -221,7 +221,7 @@ namespace MIPSComp {
// CC might be set by slow path below, so load regs first.
fpr.MapRegV(vt, MAP_DIRTY | MAP_NOINIT);
if (gpr.IsImm(rs)) {
u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
u32 addr = offset + gpr.GetImm(rs);
gpr.SetRegImm(SCRATCH1, addr);
} else {
gpr.MapReg(rs);
@@ -250,7 +250,7 @@ namespace MIPSComp {
// CC might be set by slow path below, so load regs first.
fpr.MapRegV(vt);
if (gpr.IsImm(rs)) {
u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
u32 addr = offset + gpr.GetImm(rs);
gpr.SetRegImm(SCRATCH1, addr);
} else {
gpr.MapReg(rs);
@@ -291,7 +291,7 @@ namespace MIPSComp {
fpr.MapRegsAndSpillLockV(vregs, V_Quad, MAP_DIRTY | MAP_NOINIT);
if (gpr.IsImm(rs)) {
u32 addr = (imm + gpr.GetImm(rs)) & 0x3FFFFFFF;
u32 addr = imm + gpr.GetImm(rs);
gpr.SetRegImm(SCRATCH1_64, addr + (uintptr_t)Memory::base);
} else {
gpr.MapReg(rs);
@@ -324,7 +324,7 @@ namespace MIPSComp {
fpr.MapRegsAndSpillLockV(vregs, V_Quad, 0);
if (gpr.IsImm(rs)) {
u32 addr = (imm + gpr.GetImm(rs)) & 0x3FFFFFFF;
u32 addr = imm + gpr.GetImm(rs);
gpr.SetRegImm(SCRATCH1_64, addr + (uintptr_t)Memory::base);
} else {
gpr.MapReg(rs);

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