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x64: Enable non-RIP addressing for FPU registers

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hrydgard committed Jul 7, 2017
1 parent 381c4ca commit 567937fa4db3633492b8cdf33a467a244dca8514
Showing with 19 additions and 8 deletions.
  1. +2 −0 Common/x64Emitter.h
  2. +1 −1 Core/MIPS/x86/Jit.cpp
  3. +14 −6 Core/MIPS/x86/RegCacheFPU.cpp
  4. +2 −1 Core/MIPS/x86/RegCacheFPU.h
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@@ -1072,6 +1072,8 @@ class XCodeBlock : public CodeBlock<XEmitter> {
public:
void PoisonMemory(int offset) override;
bool RipAccessible(const void *ptr) const {
// For debugging
// return false;
#ifdef _M_IX86
return true;
#else
View
@@ -355,7 +355,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b) {
MIPSAnalyst::AnalysisResults analysis = MIPSAnalyst::Analyze(em_address);
gpr.Start(mips_, &js, &jo, analysis);
fpr.Start(mips_, &js, &jo, analysis);
fpr.Start(mips_, &js, &jo, analysis, RipAccessible(&mips_->v[0]));
js.numInstructions = 0;
while (js.compiling) {
@@ -37,9 +37,9 @@ FPURegCache::FPURegCache() : mips(0), initialReady(false), emit(0) {
vregs = regs + 32;
}
void FPURegCache::Start(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo, MIPSAnalyst::AnalysisResults &stats) {
void FPURegCache::Start(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo, MIPSAnalyst::AnalysisResults &stats, bool useRip) {
this->mips = mips;
useRip_ = useRip;
if (!initialReady) {
SetupInitialRegs();
initialReady = true;
@@ -892,13 +892,21 @@ void FPURegCache::Flush() {
OpArg FPURegCache::GetDefaultLocation(int reg) const {
if (reg < 32) {
// Smaller than RIP addressing since we can use a byte offset.
return MDisp(CTXREG, reg * 4);
} else if (reg < 32 + 128) {
return M(&mips->v[voffset[reg - 32]]);
// This should work, but doesn't seem to (crashes Crisis Core). Seems a bad instruction is generated somehow...
// return MIPSSTATE_VAR(v[voffset[reg - 32]]);
// Here, RIP has the advantage so let's use it when possible
if (useRip_) {
return M(&mips->v[voffset[reg - 32]]);
} else {
return MIPSSTATE_VAR(v[voffset[reg - 32]]);
}
} else {
return MIPSSTATE_VAR(tempValues[reg - 32 - 128]);
if (useRip_) {
return M(&mips->tempValues[reg - 32 - 128]);
} else {
return MIPSSTATE_VAR(tempValues[reg - 32 - 128]);
}
}
}
@@ -97,7 +97,7 @@ class FPURegCache
FPURegCache();
~FPURegCache() {}
void Start(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo, MIPSAnalyst::AnalysisResults &stats);
void Start(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo, MIPSAnalyst::AnalysisResults &stats, bool useRip);
void MapReg(int preg, bool doLoad = true, bool makeDirty = true);
void StoreFromRegister(int preg);
void StoreFromRegisterV(int preg) {
@@ -231,6 +231,7 @@ class FPURegCache
X64CachedFPReg xregs[NUM_X_FPREGS];
MIPSCachedFPReg *vregs;
bool useRip_;
bool pendingFlush;
bool initialReady;
MIPSCachedFPReg regsInitial[NUM_MIPS_FPRS];

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