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irjit: Add dedicated ops for lwl/swl and friends.

Temporarily removes optimizations.
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unknownbrackets committed Jan 7, 2018
1 parent cd3f488 commit 6dda0533651bd732aa92d8c4edeb2f979644a06f
Showing with 60 additions and 2 deletions.
  1. +6 −2 Core/MIPS/IR/IRCompLoadStore.cpp
  2. +8 −0 Core/MIPS/IR/IRInst.cpp
  3. +8 −0 Core/MIPS/IR/IRInst.h
  4. +38 −0 Core/MIPS/IR/IRInterpreter.cpp
@@ -198,12 +198,16 @@ namespace MIPSComp {
break;
case 34: //lwl
ir.Write(IROp::Load32Left, rt, rs, ir.AddConstant(offset));
break;
case 38: //lwr
Comp_ITypeMemLR(op, true);
ir.Write(IROp::Load32Right, rt, rs, ir.AddConstant(offset));
break;
case 42: //swl
ir.Write(IROp::Store32Left, rt, rs, ir.AddConstant(offset));
break;
case 46: //swr
Comp_ITypeMemLR(op, false);
ir.Write(IROp::Store32Right, rt, rs, ir.AddConstant(offset));
break;
default:
View
@@ -71,11 +71,15 @@ static const IRMeta irMeta[] = {
{ IROp::Load16, "Load16", "GGC" },
{ IROp::Load16Ext, "Load16Ext", "GGC" },
{ IROp::Load32, "Load32", "GGC" },
{ IROp::Load32Left, "Load32Left", "GGC", IRFLAG_SRC3DST },
{ IROp::Load32Right, "Load32Right", "GGC", IRFLAG_SRC3DST },
{ IROp::LoadFloat, "LoadFloat", "FGC" },
{ IROp::LoadVec4, "LoadVec4", "VGC" },
{ IROp::Store8, "Store8", "GGC", IRFLAG_SRC3 },
{ IROp::Store16, "Store16", "GGC", IRFLAG_SRC3 },
{ IROp::Store32, "Store32", "GGC", IRFLAG_SRC3 },
{ IROp::Store32Left, "Store32Left", "GGC", IRFLAG_SRC3 },
{ IROp::Store32Right, "Store32Right", "GGC", IRFLAG_SRC3 },
{ IROp::StoreFloat, "StoreFloat", "FGC", IRFLAG_SRC3 },
{ IROp::StoreVec4, "StoreVec4", "VGC", IRFLAG_SRC3 },
{ IROp::FAdd, "FAdd", "FFF" },
@@ -206,6 +210,10 @@ const char *GetGPRName(int r) {
case IRTEMP_3: return "irtemp3";
case IRTEMP_LHS: return "irtemp_lhs";
case IRTEMP_RHS: return "irtemp_rhs";
case IRTEMP_LR_ADDR: return "irtemp_addr";
case IRTEMP_LR_VALUE: return "irtemp_value";
case IRTEMP_LR_MASK: return "irtemp_mask";
case IRTEMP_LR_SHIFT: return "irtemp_shift";
default: return "(unk)";
}
}
View
@@ -90,12 +90,16 @@ enum class IROp : u8 {
Load16,
Load16Ext,
Load32,
Load32Left,
Load32Right,
LoadFloat,
LoadVec4,
Store8,
Store16,
Store32,
Store32Left,
Store32Right,
StoreFloat,
StoreVec4,
@@ -279,6 +283,10 @@ enum {
IRTEMP_3,
IRTEMP_LHS, // Reserved for use in branches
IRTEMP_RHS, // Reserved for use in branches
IRTEMP_LR_ADDR, // Reserved for left/right loads and stores.
IRTEMP_LR_VALUE, // Reserved for left/right loads and stores.
IRTEMP_LR_MASK, // Reserved for left/right loads and stores.
IRTEMP_LR_SHIFT, // Reserved for left/right loads and stores.
IRVTEMP_PFX_S = 224 - 32, // Relative to the FP regs
IRVTEMP_PFX_T = 228 - 32,
@@ -145,6 +145,24 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
case IROp::Load32:
mips->r[inst->dest] = Memory::ReadUnchecked_U32(mips->r[inst->src1] + inst->constant);
break;
case IROp::Load32Left:
{
u32 addr = mips->r[inst->src1] + inst->constant;
u32 shift = (addr & 3) * 8;
u32 mem = Memory::ReadUnchecked_U32(addr & 0xfffffffc);
u32 destMask = 0x00ffffff >> shift;
mips->r[inst->dest] = (mips->r[inst->dest] & destMask) | (mem << (24 - shift));
break;
}
case IROp::Load32Right:
{
u32 addr = mips->r[inst->src1] + inst->constant;
u32 shift = (addr & 3) * 8;
u32 mem = Memory::ReadUnchecked_U32(addr & 0xfffffffc);
u32 destMask = 0xffffff00 << (24 - shift);
mips->r[inst->dest] = (mips->r[inst->dest] & destMask) | (mem >> shift);
break;
}
case IROp::LoadFloat:
mips->f[inst->dest] = Memory::ReadUnchecked_Float(mips->r[inst->src1] + inst->constant);
break;
@@ -158,6 +176,26 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
case IROp::Store32:
Memory::WriteUnchecked_U32(mips->r[inst->src3], mips->r[inst->src1] + inst->constant);
break;
case IROp::Store32Left:
{
u32 addr = mips->r[inst->src1] + inst->constant;
u32 shift = (addr & 3) * 8;
u32 mem = Memory::ReadUnchecked_U32(addr & 0xfffffffc);
u32 memMask = 0xffffff00 << shift;
u32 result = (mips->r[inst->src3] >> (24 - shift)) | (mem & memMask);
Memory::WriteUnchecked_U32(result, addr & 0xfffffffc);
break;
}
case IROp::Store32Right:
{
u32 addr = mips->r[inst->src1] + inst->constant;
u32 shift = (addr & 3) * 8;
u32 mem = Memory::ReadUnchecked_U32(addr & 0xfffffffc);
u32 memMask = 0x00ffffff >> (24 - shift);
u32 result = (mips->r[inst->src3] << shift) | (mem & memMask);
Memory::WriteUnchecked_U32(result, addr & 0xfffffffc);
break;
}
case IROp::StoreFloat:
Memory::WriteUnchecked_Float(mips->f[inst->src3], mips->r[inst->src1] + inst->constant);
break;

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