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arm64jit: Handle more imm compare cases.

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unknownbrackets committed Dec 29, 2017
1 parent b59c0d0 commit 7f8a871e306701b19c9adbd7ad6cddb0fe6e9d5e
Showing with 14 additions and 4 deletions.
  1. +14 −4 Core/MIPS/ARM64/Arm64CompBranch.cpp
@@ -129,10 +129,20 @@ void Arm64Jit::BranchRSRTComp(MIPSOpcode op, CCFlags cc, bool likely)
// We might be able to flip the condition (EQ/NEQ are easy.)
const bool canFlip = cc == CC_EQ || cc == CC_NEQ;
// TODO ARM64: Optimize for immediates other than zero
if (rt == 0) {
gpr.MapIn(rs);
CMP(gpr.R(rs), 0);
u32 val;
bool shift;
if (gpr.IsImm(rt) && IsImmArithmetic(gpr.GetImm(rt), &val, &shift)) {
gpr.MapReg(rs);
CMP(gpr.R(rs), val, shift);
} else if (gpr.IsImm(rt) && IsImmArithmetic((u64)(s64)-(s32)gpr.GetImm(rt), &val, &shift)) {
gpr.MapReg(rs);
CMN(gpr.R(rs), val, shift);
} else if (gpr.IsImm(rs) && IsImmArithmetic(gpr.GetImm(rs), &val, &shift) && canFlip) {
gpr.MapReg(rt);
CMP(gpr.R(rt), val, shift);
} else if (gpr.IsImm(rs) && IsImmArithmetic((u64)(s64)-(s32)gpr.GetImm(rs), &val, &shift) && canFlip) {
gpr.MapReg(rt);
CMN(gpr.R(rt), val, shift);
} else {
gpr.MapInIn(rs, rt);
CMP(gpr.R(rs), gpr.R(rt));

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