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irjit: Cleanup some invalid op handling.

And log blocks the same way as other backends.
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unknownbrackets committed Jan 1, 2018
1 parent d8d174f commit 905d2c2da6564a6976eac7c1c37a9ce6f0546ec1
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@@ -40,14 +40,15 @@
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define DISABLE { Comp_Generic(op); return; }
#define INVALIDOP { Comp_Generic(op); return; }
namespace MIPSComp {
void IRFrontend::Comp_IType(MIPSOpcode op) {
CONDITIONAL_DISABLE;
s32 simm = (s32)(s16)(op & 0xFFFF); // sign extension
u32 uimm = op & 0xFFFF;
s32 simm = (s32)_IMM16; // sign extension
u32 uimm = (u16)_IMM16;
u32 suimm = (u32)(s32)simm;
MIPSGPReg rt = _RT;
@@ -80,7 +81,7 @@ void IRFrontend::Comp_IType(MIPSOpcode op) {
break;
default:
Comp_Generic(op);
INVALIDOP;
break;
}
}
@@ -104,7 +105,7 @@ void IRFrontend::Comp_RType2(MIPSOpcode op) {
ir.Write(IROp::Clz, rd, IRTEMP_0);
break;
default:
Comp_Generic(op);
INVALIDOP;
break;
}
}
@@ -176,7 +177,7 @@ void IRFrontend::Comp_RType3(MIPSOpcode op) {
break;
default:
Comp_Generic(op);
INVALIDOP;
break;
}
}
@@ -213,8 +214,9 @@ void IRFrontend::Comp_ShiftType(MIPSOpcode op) {
case 4: CompShiftVar(op, IROp::Shl, IROp::ShlImm); break; //sllv
case 6: CompShiftVar(op, (sa == 1 ? IROp::Ror : IROp::Shr), (sa == 1 ? IROp::RorImm : IROp::ShrImm)); break; //srlv
case 7: CompShiftVar(op, IROp::Sar, IROp::SarImm); break; //srav
default:
Comp_Generic(op);
INVALIDOP;
break;
}
}
@@ -256,7 +258,7 @@ void IRFrontend::Comp_Special3(MIPSOpcode op) {
break;
default:
Comp_Generic(op);
INVALIDOP;
break;
}
}
@@ -285,7 +287,7 @@ void IRFrontend::Comp_Allegrex(MIPSOpcode op) {
break;
default:
Comp_Generic(op);
INVALIDOP;
return;
}
}
@@ -307,7 +309,7 @@ void IRFrontend::Comp_Allegrex2(MIPSOpcode op) {
ir.Write(IROp::BSwap32, rd, rt);
break;
default:
Comp_Generic(op);
INVALIDOP;
break;
}
}
@@ -372,7 +374,7 @@ void IRFrontend::Comp_MulDivType(MIPSOpcode op) {
break;
default:
DISABLE;
INVALIDOP;
}
}
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@@ -51,6 +51,7 @@
// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
#define CONDITIONAL_DISABLE ;
#define DISABLE { Comp_Generic(op); return; }
#define INVALIDOP { Comp_Generic(op); return; }
namespace MIPSComp {
@@ -67,7 +68,7 @@ void IRFrontend::Comp_FPU3op(MIPSOpcode op) {
case 2: ir.Write(IROp::FMul, fd, fs, ft); break; //F(fd) = F(fs) * F(ft); //mul
case 3: ir.Write(IROp::FDiv, fd, fs, ft); break; //F(fd) = F(fs) / F(ft); //div
default:
DISABLE;
INVALIDOP;
return;
}
}
@@ -90,7 +91,7 @@ void IRFrontend::Comp_FPULS(MIPSOpcode op) {
break;
default:
_dbg_assert_msg_(CPU, 0, "Trying to interpret FPULS instruction that can't be interpreted");
INVALIDOP;
break;
}
}
@@ -131,7 +132,7 @@ void IRFrontend::Comp_FPUComp(MIPSOpcode op) {
mode = IRFpCompareMode::LessEqualUnordered;
break;
default:
DISABLE;
INVALIDOP;
return;
}
ir.Write(IROp::FCmp, (int)mode, fs, ft);
@@ -158,27 +159,17 @@ void IRFrontend::Comp_FPU2op(MIPSOpcode op) {
break;
case 12: //FsI(fd) = (int)floorf(F(fs)+0.5f); break; //round.w.s
{
ir.Write(IROp::FRound, fd, fs);
break;
}
case 13: //FsI(fd) = Rto0(F(fs))); break; //trunc.w.s
{
ir.Write(IROp::FTrunc, fd, fs);
break;
}
case 14://FsI(fd) = (int)ceilf (F(fs)); break; //ceil.w.s
{
ir.Write(IROp::FCeil, fd, fs);
break;
}
case 15: //FsI(fd) = (int)floorf(F(fs)); break; //floor.w.s
{
ir.Write(IROp::FFloor, fd, fs);
break;
}
case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
ir.Write(IROp::FCvtSW, fd, fs);
@@ -189,7 +180,7 @@ void IRFrontend::Comp_FPU2op(MIPSOpcode op) {
break;
default:
DISABLE;
INVALIDOP;
}
}
@@ -234,7 +225,7 @@ void IRFrontend::Comp_mxc1(MIPSOpcode op) {
}
return;
default:
DISABLE;
INVALIDOP;
break;
}
}
@@ -96,13 +96,16 @@ namespace MIPSComp {
case 46: //swr
DISABLE;
break;
default:
Comp_Generic(op);
INVALIDOP;
return;
}
}
void IRFrontend::Comp_Cache(MIPSOpcode op) {
CONDITIONAL_DISABLE;
// int imm = (s16)(op & 0xFFFF);
// int rs = _RS;
// int addr = R(rs) + imm;
@@ -1929,7 +1929,7 @@ namespace MIPSComp {
ir.Write(IROp::FSub, tempregs[3], sregs[2], sregs[3]);
}
} else {
DISABLE;
INVALIDOP;
}
for (int i = 0; i < n; ++i) {
@@ -279,32 +279,32 @@ void IRFrontend::DoJit(u32 em_address, std::vector<IRInst> &instructions, std::v
if (logBlocks > 0 && dontLogBlocks == 0) {
char temp2[256];
ILOG("=============== mips %08x ===============", em_address);
NOTICE_LOG(JIT, "=============== mips %08x ===============", em_address);
for (u32 cpc = em_address; cpc != GetCompilerPC() + 4; cpc += 4) {
temp2[0] = 0;
MIPSDisAsm(Memory::Read_Opcode_JIT(cpc), cpc, temp2, true);
ILOG("M: %08x %s", cpc, temp2);
NOTICE_LOG(JIT, "M: %08x %s", cpc, temp2);
}
}
if (logBlocks > 0 && dontLogBlocks == 0) {
ILOG("=============== Original IR (%d instructions, %d const) ===============", (int)ir.GetInstructions().size(), (int)ir.GetConstants().size());
NOTICE_LOG(JIT, "=============== Original IR (%d instructions, %d const) ===============", (int)ir.GetInstructions().size(), (int)ir.GetConstants().size());
for (size_t i = 0; i < ir.GetInstructions().size(); i++) {
char buf[256];
DisassembleIR(buf, sizeof(buf), ir.GetInstructions()[i], &ir.GetConstants()[0]);
ILOG("%s", buf);
NOTICE_LOG(JIT, "%s", buf);
}
ILOG("=============== end =================");
NOTICE_LOG(JIT, "=============== end =================");
}
if (logBlocks > 0 && dontLogBlocks == 0) {
ILOG("=============== IR (%d instructions, %d const) ===============", (int)code->GetInstructions().size(), (int)code->GetConstants().size());
NOTICE_LOG(JIT, "=============== IR (%d instructions, %d const) ===============", (int)code->GetInstructions().size(), (int)code->GetConstants().size());
for (size_t i = 0; i < code->GetInstructions().size(); i++) {
char buf[256];
DisassembleIR(buf, sizeof(buf), code->GetInstructions()[i], &code->GetConstants()[0]);
ILOG("%s", buf);
NOTICE_LOG(JIT, "%s", buf);
}
ILOG("=============== end =================");
NOTICE_LOG(JIT, "=============== end =================");
}
if (logBlocks > 0)

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