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arm64jit: Use CMN for CMPI2R if possible.

It's not hit all that often, but it is hit.
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unknownbrackets committed Dec 29, 2017
1 parent 56d64f5 commit b59c0d0b45db3d98f4627891666bb53867014919
Showing with 9 additions and 0 deletions.
  1. +8 −0 Common/Arm64Emitter.cpp
  2. +1 −0 Common/Arm64Emitter.h
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@@ -1547,6 +1547,10 @@ void ARM64XEmitter::CMP(ARM64Reg Rn, u32 imm, bool shift)
{
EncodeAddSubImmInst(1, true, shift, imm, Rn, Is64Bit(Rn) ? SP : WSP);
}
void ARM64XEmitter::CMN(ARM64Reg Rn, u32 imm, bool shift)
{
EncodeAddSubImmInst(0, true, shift, imm, Rn, Is64Bit(Rn) ? SP : WSP);
}
// Data Processing (Immediate)
void ARM64XEmitter::MOVZ(ARM64Reg Rd, u32 imm, ShiftAmount pos)
@@ -3754,11 +3758,15 @@ bool ARM64XEmitter::TrySUBI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm) {
}
bool ARM64XEmitter::TryCMPI2R(ARM64Reg Rn, u64 imm) {
s64 negated = Is64Bit(Rn) ? -(s64)imm : -(s32)(u32)imm;
u32 val;
bool shift;
if (IsImmArithmetic(imm, &val, &shift)) {
CMP(Rn, val, shift);
return true;
} else if (IsImmArithmetic((u64)negated, &val, &shift)) {
CMN(Rn, val, shift);
return true;
} else {
return false;
}
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@@ -591,6 +591,7 @@ class ARM64XEmitter
void SUB(ARM64Reg Rd, ARM64Reg Rn, u32 imm, bool shift = false);
void SUBS(ARM64Reg Rd, ARM64Reg Rn, u32 imm, bool shift = false);
void CMP(ARM64Reg Rn, u32 imm, bool shift = false);
void CMN(ARM64Reg Rn, u32 imm, bool shift = false);
// Data Processing (Immediate)
void MOVZ(ARM64Reg Rd, u32 imm, ShiftAmount pos = SHIFT_0);

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