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Simplifications and fixes
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hrydgard committed May 13, 2016
1 parent 5923013 commit b7091a8
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Showing 3 changed files with 28 additions and 43 deletions.
4 changes: 2 additions & 2 deletions Core/CoreTiming.cpp
Expand Up @@ -567,12 +567,12 @@ void MoveEvents()

void ForceCheck()
{
int cyclesExecuted = slicelength - currentMIPS->downcount + 1;
int cyclesExecuted = slicelength - currentMIPS->downcount;
globalTimer += cyclesExecuted;
// This will cause us to check for new events immediately.
currentMIPS->downcount = -1;
// But let's not eat a bunch more time in Advance() because of this.
slicelength = 0;
slicelength = 1;
}

void Advance()
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23 changes: 18 additions & 5 deletions Core/MIPS/IR/IRCompVFPU.cpp
Expand Up @@ -128,12 +128,12 @@ namespace MIPSComp {

// Some common vector prefixes
if (sz == V_Quad && IsConsecutive4(vregs)) {
if (prefix == 0xF00E4 && IsConsecutive4(vregs)) {
if (prefix == 0xF00E4) {
InitRegs(vregs, tempReg);
ir.Write(IROp::Vec4Neg, vregs[0], origV[0]);
return;
}
if (prefix == 0x00FE4 && IsConsecutive4(vregs)) {
if (prefix == 0x00FE4) {
InitRegs(vregs, tempReg);
ir.Write(IROp::Vec4Abs, vregs[0], origV[0]);
return;
Expand Down Expand Up @@ -1123,7 +1123,7 @@ namespace MIPSComp {
GetVectorRegs(dregs, sz, _VD);

// SIMD-optimized implementations - if sregs[0..3] is consecutive, the rest are too.
if (msz == M_4x4 && IsConsecutive4(sregs) && IsConsecutive4(dregs)) {
if (msz == M_4x4 && IsConsecutive4(sregs)) {
int s0 = IRVTEMP_0;
int s1 = IRVTEMP_PFX_T;
if (!IsConsecutive4(tregs)) {
Expand All @@ -1136,13 +1136,26 @@ namespace MIPSComp {
ir.Write(IROp::Vec4Add, s0, s0, sregs[i * 4]);
}
}
ir.Write(IROp::Vec4Mov, dregs[0], s0);

if (IsConsecutive4(dregs)) {
ir.Write(IROp::Vec4Mov, dregs[0], s0);
} else {
for (int i = 0; i < 4; i++) {
ir.Write(IROp::FMov, dregs[i], s0 + i);
}
}
return;
} else if (!homogenous) {
for (int i = 0; i < 4; i++) {
ir.Write(IROp::Vec4Dot, s0 + i, sregs[i * 4], tregs[0]);
}
ir.Write(IROp::Vec4Mov, dregs[0], s0);
if (IsConsecutive4(dregs)) {
ir.Write(IROp::Vec4Mov, dregs[0], s0);
} else {
for (int i = 0; i < 4; i++) {
ir.Write(IROp::FMov, dregs[i], s0 + i);
}
}
return;
}
} else if (msz == M_4x4) {
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44 changes: 8 additions & 36 deletions Core/MIPS/IR/IRPassSimplify.cpp
Expand Up @@ -120,28 +120,15 @@ bool OptimizeFPMoves(const IRWriter &in, IRWriter &out) {
break;

default:
// Remap constants to the new reality
const IRMeta *m = GetIRMeta(inst.op);
switch (m->types[0]) {
case 'C':
inst.dest = out.AddConstant(constants[inst.dest]);
break;
}
switch (m->types[1]) {
case 'C':
inst.src1 = out.AddConstant(constants[inst.src1]);
break;
}
switch (m->types[2]) {
case 'C':
inst.src2 = out.AddConstant(constants[inst.src2]);
break;
}
out.Write(inst);
break;
}
prev = inst;
}
// Can reuse the old constants array - not touching constants in this pass.
for (u32 value : in.GetConstants()) {
out.AddConstant(value);
}
return logBlocks;
}

Expand Down Expand Up @@ -177,28 +164,13 @@ bool ThreeOpToTwoOp(const IRWriter &in, IRWriter &out) {
}
break;
default:
{
// Remap constants to the new reality
const IRMeta *m = GetIRMeta(inst.op);
switch (m->types[0]) {
case 'C':
inst.dest = out.AddConstant(constants[inst.dest]);
break;
}
switch (m->types[1]) {
case 'C':
inst.src1 = out.AddConstant(constants[inst.src1]);
break;
}
switch (m->types[2]) {
case 'C':
inst.src2 = out.AddConstant(constants[inst.src2]);
break;
}
out.Write(inst);
break;
}
}
}
// Can reuse the old constants array - not touching constants in this pass.
for (u32 value : in.GetConstants()) {
out.AddConstant(value);
}
return logBlocks;
}
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