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Buildfix for platforms with standards-compliant offsetof (no dynamic …

…indexing allowed)k
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hrydgard committed Jul 7, 2017
1 parent f5e1100 commit e5a7d0df9556f0ecd82f1a0cfe1413fe1008f9b9
Showing with 8 additions and 8 deletions.
  1. +1 −1 Core/MIPS/MIPS.h
  2. +5 −5 Core/MIPS/x86/CompVFPU.cpp
  3. +2 −2 Core/MIPS/x86/RegCacheFPU.cpp
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@@ -157,7 +157,7 @@ enum class CPUCore;
// Workaround for compilers that don't like dynamic indexing in offsetof
#define MIPSSTATE_VAR_ELEM32(x, i) MDisp(X64JitConstants::CTXREG, \
(int)(offsetof(MIPSState, x) - offsetof(MIPSState, f[0]) + i * 4)
(int)(offsetof(MIPSState, x) - offsetof(MIPSState, f[0]) + i * 4))
// To get RIP/relative addressing (requires tight memory control so generated code isn't too far from the binary, and a reachable variable called mips):
// #define MIPSSTATE_VAR(x) M(&mips->x)
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@@ -1465,7 +1465,7 @@ void Jit::Comp_Vcmp(MIPSOpcode op) {
MOV(32, R(TEMPREG), MIPSSTATE_VAR(vcmpResult[0]));
for (int i = 1; i < n; ++i) {
OR(32, R(TEMPREG), MIPSSTATE_VAR(vcmpResult[i]));
OR(32, R(TEMPREG), MIPSSTATE_VAR_ELEM32(vcmpResult[0], i));
}
// Aggregate the bits. Urgh, expensive. Can optimize for the case of one comparison,
@@ -2441,7 +2441,7 @@ void Jit::Comp_Mftv(MIPSOpcode op) {
// In case we have a saved prefix.
FlushPrefixV();
gpr.MapReg(rt, false, true);
MOV(32, gpr.R(rt), MIPSSTATE_VAR(vfpuCtrl[imm - 128]));
MOV(32, gpr.R(rt), MIPSSTATE_VAR_ELEM32(vfpuCtrl[0], imm - 128));
}
} else {
//ERROR - maybe need to make this value too an "interlock" value?
@@ -2473,7 +2473,7 @@ void Jit::Comp_Mftv(MIPSOpcode op) {
}
} else {
gpr.MapReg(rt, true, false);
MOV(32, MIPSSTATE_VAR(vfpuCtrl[imm - 128]), gpr.R(rt));
MOV(32, MIPSSTATE_VAR_ELEM32(vfpuCtrl[0], imm - 128), gpr.R(rt));
}
// TODO: Optimization if rt is Imm?
@@ -2505,7 +2505,7 @@ void Jit::Comp_Vmfvc(MIPSOpcode op) {
gpr.MapReg(MIPS_REG_VFPUCC, true, false);
MOVD_xmm(fpr.VX(vs), gpr.R(MIPS_REG_VFPUCC));
} else {
MOVSS(fpr.VX(vs), MIPSSTATE_VAR(vfpuCtrl[imm - 128]));
MOVSS(fpr.VX(vs), MIPSSTATE_VAR_ELEM32(vfpuCtrl[0], imm - 128));
}
fpr.ReleaseSpillLocks();
}
@@ -2521,7 +2521,7 @@ void Jit::Comp_Vmtvc(MIPSOpcode op) {
gpr.MapReg(MIPS_REG_VFPUCC, false, true);
MOVD_xmm(gpr.R(MIPS_REG_VFPUCC), fpr.VX(vs));
} else {
MOVSS(MIPSSTATE_VAR(vfpuCtrl[imm - 128]), fpr.VX(vs));
MOVSS(MIPSSTATE_VAR_ELEM32(vfpuCtrl[0], imm - 128), fpr.VX(vs));
}
fpr.ReleaseSpillLocks();
@@ -899,13 +899,13 @@ OpArg FPURegCache::GetDefaultLocation(int reg) const {
if (useRip_) {
return M(&mips->v[voffset[reg - 32]]); // rip accessible
} else {
return MIPSSTATE_VAR(v[voffset[reg - 32]]); // rip accessible
return MIPSSTATE_VAR_ELEM32(v[0], voffset[reg - 32]); // rip accessible
}
} else {
if (useRip_) {
return M(&mips->tempValues[reg - 32 - 128]);
} else {
return MIPSSTATE_VAR(tempValues[reg - 32 - 128]);
return MIPSSTATE_VAR_ELEM32(tempValues[0], reg - 32 - 128);
}
}
}

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