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arm64jit: Cleanup method names, temp discard.

This way MapDirtyIn won't accidentally discard temps.
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unknownbrackets committed Dec 30, 2017
1 parent eb35e88 commit e7ac6725224e9afb945b7abe048add2aec83c8ac
Showing with 25 additions and 18 deletions.
  1. +5 −5 Core/MIPS/ARM64/Arm64CompLoadStore.cpp
  2. +16 −10 Core/MIPS/ARM64/Arm64RegCache.cpp
  3. +4 −3 Core/MIPS/ARM64/Arm64RegCache.h
@@ -250,7 +250,7 @@ namespace MIPSComp {
SetJumpTarget(skip);
}
gpr.ReleaseSpillLocks();
gpr.ReleaseSpillLocksAndDiscardTemps();
}
void Arm64Jit::Comp_ITypeMem(MIPSOpcode op) {
@@ -311,7 +311,7 @@ namespace MIPSComp {
gpr.MapRegAsPointer(rs);
// For a store, try to avoid mapping a reg if not needed.
targetReg = load ? INVALID_REG : gpr.MapTempImm(rt);
targetReg = load ? INVALID_REG : gpr.TryMapTempImm(rt);
if (targetReg == INVALID_REG) {
gpr.MapReg(rt, load ? MAP_NOINIT : 0);
targetReg = gpr.R(rt);
@@ -327,20 +327,20 @@ namespace MIPSComp {
case 41: STRH(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
case 40: STRB(INDEX_UNSIGNED, targetReg, gpr.RPtr(rs), offset); break;
}
gpr.ReleaseSpillLocks();
gpr.ReleaseSpillLocksAndDiscardTemps();
break;
}
}
if (!load && gpr.IsImm(rt) && gpr.MapTempImm(rt) != INVALID_REG) {
if (!load && gpr.IsImm(rt) && gpr.TryMapTempImm(rt) != INVALID_REG) {
// We're storing an immediate value, let's see if we can optimize rt.
if (!gpr.IsImm(rs) || offset == 0) {
// In this case, we're always going to need rs mapped, which may flush the temp imm.
// We handle that in the cases below since targetReg is INVALID_REG.
gpr.MapIn(rs);
}
targetReg = gpr.MapTempImm(rt);
targetReg = gpr.TryMapTempImm(rt);
}
if (gpr.IsImm(rs) && Memory::IsValidAddress(iaddr)) {
@@ -304,7 +304,7 @@ ARM64Reg Arm64RegCache::FindBestToSpill(bool unusedOnly, bool *clobbered) {
return INVALID_REG;
}
ARM64Reg Arm64RegCache::MapTempImm(MIPSGPReg r) {
ARM64Reg Arm64RegCache::TryMapTempImm(MIPSGPReg r) {
// If already mapped, no need for a temporary.
if (IsMapped(r)) {
return R(r);
@@ -459,15 +459,15 @@ void Arm64RegCache::MapInIn(MIPSGPReg rd, MIPSGPReg rs) {
SpillLock(rd, rs);
MapReg(rd);
MapReg(rs);
ReleaseSpillLocks();
ReleaseSpillLock(rd, rs);
}
void Arm64RegCache::MapDirtyIn(MIPSGPReg rd, MIPSGPReg rs, bool avoidLoad) {
SpillLock(rd, rs);
bool load = !avoidLoad || rd == rs;
MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);
MapReg(rs);
ReleaseSpillLocks();
ReleaseSpillLock(rd, rs);
}
void Arm64RegCache::MapDirtyInIn(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, bool avoidLoad) {
@@ -476,7 +476,7 @@ void Arm64RegCache::MapDirtyInIn(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, bool
MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);
MapReg(rt);
MapReg(rs);
ReleaseSpillLocks();
ReleaseSpillLock(rd, rs, rt);
}
void Arm64RegCache::MapDirtyDirtyIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs, bool avoidLoad) {
@@ -486,7 +486,7 @@ void Arm64RegCache::MapDirtyDirtyIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs,
MapReg(rd1, load1 ? MAP_DIRTY : MAP_NOINIT);
MapReg(rd2, load2 ? MAP_DIRTY : MAP_NOINIT);
MapReg(rs);
ReleaseSpillLocks();
ReleaseSpillLock(rd1, rd2, rs);
}
void Arm64RegCache::MapDirtyDirtyInIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs, MIPSGPReg rt, bool avoidLoad) {
@@ -497,7 +497,7 @@ void Arm64RegCache::MapDirtyDirtyInIn(MIPSGPReg rd1, MIPSGPReg rd2, MIPSGPReg rs
MapReg(rd2, load2 ? MAP_DIRTY : MAP_NOINIT);
MapReg(rt);
MapReg(rs);
ReleaseSpillLocks();
ReleaseSpillLock(rd1, rd2, rs, rt);
}
void Arm64RegCache::FlushArmReg(ARM64Reg r) {
@@ -872,7 +872,7 @@ void Arm64RegCache::SpillLock(MIPSGPReg r1, MIPSGPReg r2, MIPSGPReg r3, MIPSGPRe
if (r4 != MIPS_REG_INVALID) mr[r4].spillLock = true;
}
void Arm64RegCache::ReleaseSpillLocks() {
void Arm64RegCache::ReleaseSpillLocksAndDiscardTemps() {
for (int i = 0; i < NUM_MIPSREG; i++) {
if (!mr[i].isStatic)
mr[i].spillLock = false;
@@ -882,9 +882,15 @@ void Arm64RegCache::ReleaseSpillLocks() {
}
}
void Arm64RegCache::ReleaseSpillLock(MIPSGPReg reg) {
if (!mr[reg].isStatic)
mr[reg].spillLock = false;
void Arm64RegCache::ReleaseSpillLock(MIPSGPReg r1, MIPSGPReg r2, MIPSGPReg r3, MIPSGPReg r4) {
if (!mr[r1].isStatic)
mr[r1].spillLock = false;
if (r2 != MIPS_REG_INVALID && !mr[r2].isStatic)
mr[r2].spillLock = false;
if (r3 != MIPS_REG_INVALID && !mr[r3].isStatic)
mr[r3].spillLock = false;
if (r4 != MIPS_REG_INVALID && !mr[r4].isStatic)
mr[r4].spillLock = false;
}
ARM64Reg Arm64RegCache::R(MIPSGPReg mipsReg) {
@@ -92,8 +92,8 @@ class Arm64RegCache {
// Protect the arm register containing a MIPS register from spilling, to ensure that
// it's being kept allocated.
void SpillLock(MIPSGPReg reg, MIPSGPReg reg2 = MIPS_REG_INVALID, MIPSGPReg reg3 = MIPS_REG_INVALID, MIPSGPReg reg4 = MIPS_REG_INVALID);
void ReleaseSpillLock(MIPSGPReg reg);
void ReleaseSpillLocks();
void ReleaseSpillLock(MIPSGPReg reg, MIPSGPReg reg2 = MIPS_REG_INVALID, MIPSGPReg reg3 = MIPS_REG_INVALID, MIPSGPReg reg4 = MIPS_REG_INVALID);
void ReleaseSpillLocksAndDiscardTemps();
void SetImm(MIPSGPReg reg, u64 immVal);
bool IsImm(MIPSGPReg reg) const;
@@ -102,7 +102,8 @@ class Arm64RegCache {
// Optimally set a register to an imm value (possibly using another register.)
void SetRegImm(Arm64Gen::ARM64Reg reg, u64 imm);
Arm64Gen::ARM64Reg MapTempImm(MIPSGPReg);
// May fail and return INVALID_REG if it needs flushing.
Arm64Gen::ARM64Reg TryMapTempImm(MIPSGPReg);
// Returns an ARM register containing the requested MIPS register.
Arm64Gen::ARM64Reg MapReg(MIPSGPReg reg, int mapFlags = 0);

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