huguesb / almostrisc

Quick README for Archi2 project

 * goals :
	* write a RISC-like CPU in VHDL
	* test it on a Spartan3 FPGA with a custom program
 
 * tools : 
	* ghdl/gtkwave for simulation (through the sim script)
		
		# run testbench for 15 microseconds and display (-d)
		# results in gtkwave, using tb.sav to keep track of signals to show
		$ ./sim testbench 15us -d -s tb.sav
		
		
	* homemade modular assembler
		
		# assemble demo.asm into VHDL-compatible word-stream
		$ ./asrisc assembler/opcodes.js demo/demo.asm
		
		# assemble and directly insert output into ROMPROG.vhd
		$ ./asrom
		
	* simple wrapper script for ghdl and gtkwave (sim) :
		$ ./sim testbench 15us -d -s testbench.sav

 * specs : see cdc2010.pdf

 * extensions : see todo

 * history : 
	All recent history (after 16/02/2010) on git logs...
	
	16/02/2010 : 
		* Merged all changes of the last few days into master git branch
		* Created a public git repo on telesun (not quite public really more of a backup)
	
	15/02/2010 : history "lost" in an unnamed git branch
	14/02/2010 : history "lost" in an unnamed git branch
	13/02/2010 : history "lost" in an unnamed git branch
	
	12/02/2010 : small changes
		* Fixed small VGA bug after first TP
		* Added sim script to streamline simulation
		* Imported all project files into a Git repo
		* Some small cleanups (replacing std_logic_arith with numeric_std)
		* Fixed UAL-related instruction parsing in assembler
		
	11/02/2010 : extended test suite
		* slight changes in testbench
		* added a proof-of-concept assembler (C++/QtScript) 
		
	10/02/2010 : minor changes
		* now compiles with ghdl
		* basic FSM/PO tests (in, out, reset) using ghdl/gtkwave

	07/02/2010 : first version
		* written after basic specs
		* compiles with xilinx tools
		* untested