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CPU INFOrmation library (x86/x86-64/ARM/ARM64, Linux/Windows/Android/macOS/iOS)
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CPU INFOrmation library

BSD (2 clause) License Linux/Mac build status Windows build status

cpuinfo is a library to detect essential for performance optimization information about host CPU.


  • Cross-platform availability:
    • Linux, Windows, macOS, Android, and iOS operating systems
    • x86, x86-64, ARM, and ARM64 architectures
  • Modern C/C++ interface
    • Thread-safe
    • No memory allocation after initialization
    • No exceptions thrown
  • Detection of supported instruction sets, up to AVX512 (x86) and ARMv8.3 extensions
  • Detection of SoC and core information:
    • Processor (SoC) name
    • Vendor and microarchitecture for each CPU core
    • ID (MIDR on ARM, CPUID leaf 1 EAX value on x86) for each CPU core
  • Detection of cache information:
    • Cache type (instruction/data/unified), size and line size
    • Cache associativity
    • Cores and logical processors (hyper-threads) sharing the cache
  • Detection of topology information (relative between logical processors, cores, and processor packages)
  • Well-tested production-quality code:
    • 60+ mock tests based on data from real devices
    • Includes work-arounds for common bugs in hardware and OS kernels
    • Supports systems with heterogenous cores, such as big.LITTLE and Max.Med.Min
  • Permissive open-source license (Simplified BSD)


Log processor name:

printf("Running on %s CPU\n", cpuinfo_get_package(0)->name);

Detect if target is a 32-bit or 64-bit ARM system:

    /* 32-bit ARM-specific code here */

Check if the host CPU support ARM NEON

if (cpuinfo_has_arm_neon()) {

Check if the host CPU supports x86 AVX

if (cpuinfo_has_x86_avx()) {

Check if the thread runs on a Cortex-A53 core

switch (cpuinfo_get_current_core()->uarch) {
    case cpuinfo_uarch_cortex_a53:

Get the size of level 1 data cache on the fastest core in the processor (e.g. big core in big.LITTLE ARM systems):

const size_t l1_size = cpuinfo_get_processor(0)->cache.l1d->size;

Pin thread to cores sharing L2 cache with the current core (Linux or Android)

cpu_set_t cpu_set;
const struct cpuinfo_cache* current_l2 = cpuinfo_get_current_processor()->cache.l2;
for (uint32_t i = 0; i < current_l2->processor_count; i++) {
    CPU_SET(cpuinfo_get_processor(current_l2->processor_start + i)->linux_id, &cpu_set);
pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpu_set);

Exposed information

  • Processor (SoC) name
  • Microarchitecture
  • Usable instruction sets
  • CPU frequency
  • Cache
    • Size
    • Associativity
    • Line size
    • Number of partitions
    • Flags (unified, inclusive, complex hash function)
    • Topology (logical processors that share this cache level)
  • TLB
    • Number of entries
    • Associativity
    • Covered page types (instruction, data)
    • Covered page sizes
  • Topology information
    • Logical processors
    • Cores
    • Packages (sockets)

Supported environments:

  • Android
    • x86 ABI
    • x86_64 ABI
    • armeabi ABI
    • armeabiv7-a ABI
    • arm64-v8a ABI
    • mips ABI
    • mips64 ABI
  • Linux
    • x86
    • x86-64
    • 32-bit ARM (ARMv5T and later)
    • ARM64
    • PowerPC64
  • iOS
    • x86 (iPhone simulator)
    • x86-64 (iPhone simulator)
    • ARMv7
    • ARM64
  • OS X
    • x86
    • x86-64
  • Windows
    • x86
    • x86-64


  • Processor (SoC) name detection
    • Using CPUID leaves 0x80000002–0x80000004 on x86/x86-64
    • Using /proc/cpuinfo on ARM
    • Using ro.chipname, ro.board.platform, ro.product.board, ro.mediatek.platform, ro.arch properties (Android)
    • Using kernel log (dmesg) on ARM Linux
  • Vendor and microarchitecture detection
    • Intel-designed x86/x86-64 cores (up to Kaby Lake, Airmont, and Knights Mill)
    • AMD-designed x86/x86-64 cores (up to Puma/Jaguar and Zen)
    • VIA-designed x86/x86-64 cores
    • Other x86 cores (DM&P, RDC, Transmeta, Cyrix, Rise)
    • ARM-designed ARM cores (up to Cortex-A55 and Cortex-A75)
    • Qualcomm-designed ARM cores (up to Kryo, Kryo-280, and Kryo-385)
    • Nvidia-designed ARM cores (Denver)
    • Samsung-designed ARM cores (Mongoose and Meerkat)
    • Intel-designed ARM cores (XScale up to 3rd-gen)
    • Apple-designed ARM cores (up to Hurricane)
    • Cavium-designed ARM cores (ThunderX)
    • AppliedMicro-designed ARM cores (X-Gene)
  • Instruction set detection
    • Using CPUID (x86/x86-64)
    • Using dynamic code generation validator (Native Client/x86-64)
    • Using /proc/cpuinfo on 32-bit ARM EABI (Linux)
    • Using microarchitecture heuristics on (32-bit ARM)
    • Using FPSID and WCID registers (32-bit ARM)
    • Using getauxval (Linux/ARM)
    • Using /proc/self/auxv (Android/ARM)
    • Using instruction probing on ARM (Linux)
    • Using CPUID registers on ARM64 (Linux)
  • Cache detection
    • Using CPUID leaf 0x00000002 (x86/x86-64)
    • Using CPUID leaf 0x00000004 (non-AMD x86/x86-64)
    • Using CPUID leaves 0x80000005-0x80000006 (AMD x86/x86-64)
    • Using CPUID leaf 0x8000001D (AMD x86/x86-64)
    • Using /proc/cpuinfo (Linux/pre-ARMv7)
    • Using microarchitecture heuristics (ARM)
    • Using chipset name (ARM)
    • Using sysctlbyname (Mach)
    • Using sysfs typology directories (ARM/Linux)
    • Using sysfs cache directories (Linux)
  • TLB detection
    • Using CPUID leaf 0x00000002 (x86/x86-64)
    • Using CPUID leaves 0x80000005-0x80000006 and 0x80000019 (AMD x86/x86-64)
    • Using microarchitecture heuristics (ARM)
  • Topology detection
    • Using CPUID leaf 0x00000001 on x86/x86-64 (legacy APIC ID)
    • Using CPUID leaf 0x0000000B on x86/x86-64 (Intel APIC ID)
    • Using CPUID leaf 0x8000001E on x86/x86-64 (AMD APIC ID)
    • Using /proc/cpuinfo (Linux)
    • Using host_info (Mach)
    • Using GetLogicalProcessorInformationEx (Windows)
    • Using sysfs (Linux)
    • Using chipset name (ARM/Linux)
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