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Chisel implementation of USTC RISC-V
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README.md

USTC RISC-V

Build Status CircleCI

Chisel implementation of USTC RISC-V

TODO List

  • Hardware Design
    • Implement RISC-V RV32I ISA (user instructions)
    • Implement RISC-V RV32I ISA (privileged instructions)
    • Verify the design is running properly
    • Program implementation to Nexys4 DDR board
  • Toolchain research
    • Find out C-to-bare-metal compilation route
    • Find out how to debug RISC-V programs
  • Combined
    • Send compiled program to, and run on FPGA board
    • (Optional / Delayable) Find out how to debug FPGA from computer (may require additional hardware)
  • More TBA

Done list

  • TBA

References

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