From 64a2b78a43f15a93364ca93e1a3354260a1919a9 Mon Sep 17 00:00:00 2001 From: wtfsck Date: Sat, 12 Feb 2022 18:22:53 +0100 Subject: [PATCH 1/6] Remove local --- .../DecoderInternal/OpCodeHandlers_Legacy.cs | 54 +++++++------------ 1 file changed, 18 insertions(+), 36 deletions(-) diff --git a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs index b0425e561..99ca9f98e 100644 --- a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs +++ b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs @@ -550,8 +550,7 @@ sealed class OpCodeHandler_Ev_Iz : OpCodeHandlerModRM { else { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op0Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } if ((uint)operandSize == (uint)OpSize.Size32) { instruction.Op1Kind = OpKind.Immediate32; @@ -587,8 +586,7 @@ sealed class OpCodeHandler_Ev_Ib : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op0Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); @@ -626,8 +624,7 @@ sealed class OpCodeHandler_Ev_Ib2 : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op0Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); @@ -657,8 +654,7 @@ sealed class OpCodeHandler_Ev_1 : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op0Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -683,8 +679,7 @@ sealed class OpCodeHandler_Ev_CL : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op0Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -712,8 +707,7 @@ sealed class OpCodeHandler_Ev : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op0Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); @@ -921,8 +915,7 @@ sealed class OpCodeHandler_Evw : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op0Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -944,8 +937,7 @@ sealed class OpCodeHandler_Ew : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op0Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -999,8 +991,7 @@ sealed class OpCodeHandler_Gv_Ev : OpCodeHandlerModRM { else { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op1Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } } } @@ -1067,8 +1058,7 @@ sealed class OpCodeHandler_Gdq_Ev : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op1Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { instruction.Op1Kind = OpKind.Memory; @@ -1093,8 +1083,7 @@ sealed class OpCodeHandler_Gv_Ev3 : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op1Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { instruction.Op1Kind = OpKind.Memory; @@ -1561,8 +1550,7 @@ sealed class OpCodeHandler_Ev_Gv : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op0Register = ((int)decoder.state.operandSize << 4) + (int)index + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); @@ -1625,8 +1613,7 @@ sealed class OpCodeHandler_Ev_Gv_Ib : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op0Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -1656,8 +1643,7 @@ sealed class OpCodeHandler_Ev_Gv_CL : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op0Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -2353,8 +2339,7 @@ sealed class OpCodeHandler_Gv_Ev_Ib : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op1Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { instruction.Op1Kind = OpKind.Memory; @@ -2466,8 +2451,7 @@ sealed class OpCodeHandler_Gv_Ev_Iz : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op1Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { instruction.Op1Kind = OpKind.Memory; @@ -2802,8 +2786,7 @@ sealed class OpCodeHandler_Ev_Sw : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op0Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -2873,8 +2856,7 @@ sealed class OpCodeHandler_Sw_Ev : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - instruction.Op1Register = ((int)operandSize << 4) + (int)index + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; } else { instruction.Op1Kind = OpKind.Memory; From 149cf9677e341d7aee6e952e02960eb407378880 Mon Sep 17 00:00:00 2001 From: wtfsck Date: Sat, 12 Feb 2022 18:22:58 +0100 Subject: [PATCH 2/6] Move fields --- src/rust/iced-x86/src/decoder.rs | 4 +- .../iced-x86/src/decoder/handlers/evex.rs | 86 +++++++++--------- .../iced-x86/src/decoder/handlers/legacy.rs | 90 +++++++++---------- src/rust/iced-x86/src/decoder/handlers/vex.rs | 52 +++++------ 4 files changed, 116 insertions(+), 116 deletions(-) diff --git a/src/rust/iced-x86/src/decoder.rs b/src/rust/iced-x86/src/decoder.rs index fff99af2e..5e86bf2bf 100644 --- a/src/rust/iced-x86/src/decoder.rs +++ b/src/rust/iced-x86/src/decoder.rs @@ -525,7 +525,7 @@ struct State { aaa: u32, extra_register_base_evex: u32, // EVEX/MVEX.R' << 4 extra_base_register_base_evex: u32, // EVEX/MVEX.XB << 3 - // The order of these 4 fields are important. They're accessed as a u32 (decode_out_ptr()) by the compiler so should be 4 byte aligned. + // The order of these 4 fields is important. They're accessed as a u32 (decode_out_ptr()) by the compiler so should be 4 byte aligned. address_size: OpSize, operand_size: OpSize, segment_prio: u8, // 0=ES/CS/SS/DS, 1=FS/GS @@ -629,7 +629,7 @@ where mask_e0: u32, rex_mask: u32, bitness: u32, - // The order of these 4 fields are important. They're accessed as a u32 (decode_out_ptr()) by the compiler so should be 4 byte aligned. + // The order of these 4 fields is important. They're accessed as a u32 (decode_out_ptr()) by the compiler so should be 4 byte aligned. default_address_size: OpSize, default_operand_size: OpSize, segment_prio: u8, // Always 0 diff --git a/src/rust/iced-x86/src/decoder/handlers/evex.rs b/src/rust/iced-x86/src/decoder/handlers/evex.rs index 6bdb37877..ee202855b 100644 --- a/src/rust/iced-x86/src/decoder/handlers/evex.rs +++ b/src/rust/iced-x86/src/decoder/handlers/evex.rs @@ -96,9 +96,9 @@ impl OpCodeHandler_VectorLength_EVEX_er { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_V_H_Ev_er { has_modrm: bool, + base_reg: Register, code_w0: Code, code_w1: Code, - base_reg: Register, tuple_type_w0: TupleType, tuple_type_w1: TupleType, } @@ -160,9 +160,9 @@ impl OpCodeHandler_EVEX_V_H_Ev_er { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_V_H_Ev_Ib { has_modrm: bool, + base_reg: Register, code_w0: Code, code_w1: Code, - base_reg: Register, tuple_type_w0: TupleType, tuple_type_w1: TupleType, } @@ -213,9 +213,9 @@ impl OpCodeHandler_EVEX_V_H_Ev_Ib { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_Ed_V_Ib { has_modrm: bool, + base_reg: Register, code32: Code, code64: Code, - base_reg: Register, tuple_type32: TupleType, tuple_type64: TupleType, } @@ -268,9 +268,9 @@ impl OpCodeHandler_EVEX_Ed_V_Ib { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VkHW_er { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, - tuple_type: TupleType, only_sae: bool, can_broadcast: bool, } @@ -328,9 +328,9 @@ impl OpCodeHandler_EVEX_VkHW_er { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VkHW_er_ur { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, - tuple_type: TupleType, can_broadcast: bool, } @@ -386,10 +386,10 @@ impl OpCodeHandler_EVEX_VkHW_er_ur { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VkW_er { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, - tuple_type: TupleType, only_sae: bool, can_broadcast: bool, } @@ -464,10 +464,10 @@ impl OpCodeHandler_EVEX_VkW_er { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VkWIb_er { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_VkWIb_er { @@ -508,10 +508,10 @@ impl OpCodeHandler_EVEX_VkWIb_er { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VkW { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, - tuple_type: TupleType, can_broadcast: bool, } @@ -563,11 +563,11 @@ impl OpCodeHandler_EVEX_VkW { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_WkV { has_modrm: bool, - disallow_zeroing_masking: u32, + tuple_type: TupleType, code: Code, + disallow_zeroing_masking: u32, base_reg1: Register, base_reg2: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_WkV { @@ -632,9 +632,9 @@ impl OpCodeHandler_EVEX_WkV { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VkM { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_VkM { @@ -668,10 +668,10 @@ impl OpCodeHandler_EVEX_VkM { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VkWIb { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, - tuple_type: TupleType, can_broadcast: bool, } @@ -718,10 +718,10 @@ impl OpCodeHandler_EVEX_VkWIb { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_WkVIb { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_WkVIb { @@ -759,11 +759,11 @@ impl OpCodeHandler_EVEX_WkVIb { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_HkWIb { has_modrm: bool, + can_broadcast: bool, code: Code, base_reg1: Register, base_reg2: Register, tuple_type: TupleType, - can_broadcast: bool, } impl OpCodeHandler_EVEX_HkWIb { @@ -803,10 +803,10 @@ impl OpCodeHandler_EVEX_HkWIb { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_HWIb { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_HWIb { @@ -842,10 +842,10 @@ impl OpCodeHandler_EVEX_HWIb { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_WkVIb_er { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_WkVIb_er { @@ -887,10 +887,10 @@ impl OpCodeHandler_EVEX_WkVIb_er { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VW_er { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_VW_er { @@ -930,10 +930,10 @@ impl OpCodeHandler_EVEX_VW_er { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VW { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_VW { @@ -973,10 +973,10 @@ impl OpCodeHandler_EVEX_VW { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_WV { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_WV { @@ -1016,9 +1016,9 @@ impl OpCodeHandler_EVEX_WV { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VM { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_VM { @@ -1055,8 +1055,8 @@ impl OpCodeHandler_EVEX_VM { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VK { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_EVEX_VK { @@ -1092,8 +1092,8 @@ impl OpCodeHandler_EVEX_VK { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_KR { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_EVEX_KR { @@ -1130,9 +1130,9 @@ impl OpCodeHandler_EVEX_KR { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_KkHWIb_sae { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, - tuple_type: TupleType, can_broadcast: bool, } @@ -1180,11 +1180,11 @@ impl OpCodeHandler_EVEX_KkHWIb_sae { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VkHW { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, base_reg3: Register, - tuple_type: TupleType, can_broadcast: bool, } @@ -1237,10 +1237,10 @@ impl OpCodeHandler_EVEX_VkHW { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VkHM { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_VkHM { @@ -1275,11 +1275,11 @@ impl OpCodeHandler_EVEX_VkHM { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VkHWIb { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, base_reg3: Register, - tuple_type: TupleType, can_broadcast: bool, } @@ -1334,11 +1334,11 @@ impl OpCodeHandler_EVEX_VkHWIb { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VkHWIb_er { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg1: Register, base_reg2: Register, base_reg3: Register, - tuple_type: TupleType, can_broadcast: bool, } @@ -1386,9 +1386,9 @@ impl OpCodeHandler_EVEX_VkHWIb_er { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_KkHW { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, - tuple_type: TupleType, can_broadcast: bool, } @@ -1434,9 +1434,9 @@ impl OpCodeHandler_EVEX_KkHW { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_KP1HW { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_KP1HW { @@ -1477,9 +1477,9 @@ impl OpCodeHandler_EVEX_KP1HW { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_KkHWIb { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, - tuple_type: TupleType, can_broadcast: bool, } @@ -1527,8 +1527,8 @@ impl OpCodeHandler_EVEX_KkHWIb { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_WkHV { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_EVEX_WkHV { @@ -1559,9 +1559,9 @@ impl OpCodeHandler_EVEX_WkHV { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VHWIb { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_VHWIb { @@ -1598,12 +1598,12 @@ impl OpCodeHandler_EVEX_VHWIb { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VHW { has_modrm: bool, + tuple_type: TupleType, code_r: Code, code_m: Code, base_reg1: Register, base_reg2: Register, base_reg3: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_VHW { @@ -1650,9 +1650,9 @@ impl OpCodeHandler_EVEX_VHW { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VHM { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_VHM { @@ -1687,10 +1687,10 @@ impl OpCodeHandler_EVEX_VHM { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_Gv_W_er { has_modrm: bool, + tuple_type: TupleType, code_w0: Code, code_w1: Code, base_reg: Register, - tuple_type: TupleType, only_sae: bool, } @@ -1847,9 +1847,9 @@ impl OpCodeHandler_EVEX_Ev_VX { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_Ev_VX_Ib { has_modrm: bool, + base_reg: Register, code32: Code, code64: Code, - base_reg: Register, } impl OpCodeHandler_EVEX_Ev_VX_Ib { @@ -1888,9 +1888,9 @@ impl OpCodeHandler_EVEX_Ev_VX_Ib { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_MV { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_MV { @@ -1926,9 +1926,9 @@ impl OpCodeHandler_EVEX_MV { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VkEv_REXW { has_modrm: bool, + base_reg: Register, code32: Code, code64: Code, - base_reg: Register, } impl OpCodeHandler_EVEX_VkEv_REXW { @@ -1969,10 +1969,10 @@ impl OpCodeHandler_EVEX_VkEv_REXW { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_Vk_VSIB { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, vsib_base: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_Vk_VSIB { @@ -2011,10 +2011,10 @@ impl OpCodeHandler_EVEX_Vk_VSIB { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VSIB_k1_VX { has_modrm: bool, + tuple_type: TupleType, code: Code, vsib_index: Register, base_reg: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_VSIB_k1_VX { @@ -2050,9 +2050,9 @@ impl OpCodeHandler_EVEX_VSIB_k1_VX { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_VSIB_k1 { has_modrm: bool, + tuple_type: TupleType, code: Code, vsib_index: Register, - tuple_type: TupleType, } impl OpCodeHandler_EVEX_VSIB_k1 { @@ -2084,9 +2084,9 @@ impl OpCodeHandler_EVEX_VSIB_k1 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_GvM_VX_Ib { has_modrm: bool, + base_reg: Register, code32: Code, code64: Code, - base_reg: Register, tuple_type32: TupleType, tuple_type64: TupleType, } @@ -2139,9 +2139,9 @@ impl OpCodeHandler_EVEX_GvM_VX_Ib { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_EVEX_KkWIb { has_modrm: bool, + tuple_type: TupleType, code: Code, base_reg: Register, - tuple_type: TupleType, can_broadcast: bool, } diff --git a/src/rust/iced-x86/src/decoder/handlers/legacy.rs b/src/rust/iced-x86/src/decoder/handlers/legacy.rs index ca79b0ade..083348bb9 100644 --- a/src/rust/iced-x86/src/decoder/handlers/legacy.rs +++ b/src/rust/iced-x86/src/decoder/handlers/legacy.rs @@ -290,8 +290,8 @@ impl OpCodeHandler_PrefixF3 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_PrefixREX { has_modrm: bool, - handler: (OpCodeHandlerDecodeFn, &'static OpCodeHandler), rex: u32, + handler: (OpCodeHandlerDecodeFn, &'static OpCodeHandler), } impl OpCodeHandler_PrefixREX { @@ -335,8 +335,8 @@ impl OpCodeHandler_PrefixREX { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Reg { has_modrm: bool, - code: Code, reg: Register, + code: Code, } impl OpCodeHandler_Reg { @@ -357,8 +357,8 @@ impl OpCodeHandler_Reg { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_RegIb { has_modrm: bool, - code: Code, reg: Register, + code: Code, } impl OpCodeHandler_RegIb { @@ -381,8 +381,8 @@ impl OpCodeHandler_RegIb { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_IbReg { has_modrm: bool, - code: Code, reg: Register, + code: Code, } impl OpCodeHandler_IbReg { @@ -594,11 +594,11 @@ impl OpCodeHandler_MandatoryPrefix3 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_MandatoryPrefix4 { has_modrm: bool, + flags: u32, handler_np: (OpCodeHandlerDecodeFn, &'static OpCodeHandler), handler_66: (OpCodeHandlerDecodeFn, &'static OpCodeHandler), handler_f3: (OpCodeHandlerDecodeFn, &'static OpCodeHandler), handler_f2: (OpCodeHandlerDecodeFn, &'static OpCodeHandler), - flags: u32, } impl OpCodeHandler_MandatoryPrefix4 { @@ -704,8 +704,8 @@ impl OpCodeHandler_Reservednop { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ev_Iz { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], state_flags_or_value: u32, } @@ -758,10 +758,10 @@ impl OpCodeHandler_Ev_Iz { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ev_Ib { has_modrm: bool, + op_kinds: [OpKind; 3], reg_base: [u32; 3], - code: [Code; 3], state_flags_or_value: u32, - op_kinds: [OpKind; 3], + code: [Code; 3], } impl OpCodeHandler_Ev_Ib { @@ -806,8 +806,8 @@ impl OpCodeHandler_Ev_Ib { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ev_Ib2 { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], state_flags_or_value: u32, } @@ -852,8 +852,8 @@ impl OpCodeHandler_Ev_Ib2 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ev_1 { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Ev_1 { @@ -888,8 +888,8 @@ impl OpCodeHandler_Ev_1 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ev_CL { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Ev_CL { @@ -922,8 +922,8 @@ impl OpCodeHandler_Ev_CL { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ev { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], state_flags_or_value: u32, } @@ -966,8 +966,8 @@ impl OpCodeHandler_Ev { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Rv { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Rv { @@ -1104,10 +1104,10 @@ impl OpCodeHandler_Ev_REXW { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Evj { has_modrm: bool, - reg_base: [u32; 3], code16: Code, code32: Code, code64: Code, + reg_base: [u32; 3], } impl OpCodeHandler_Evj { @@ -1199,8 +1199,8 @@ impl OpCodeHandler_Ep { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Evw { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Evw { @@ -1232,8 +1232,8 @@ impl OpCodeHandler_Evw { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ew { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Ew { @@ -1297,8 +1297,8 @@ impl OpCodeHandler_Ms { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Gv_Ev { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Gv_Ev { @@ -1357,8 +1357,8 @@ impl OpCodeHandler_Gd_Rd { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Gv_M_as { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Gv_M_as { @@ -1391,8 +1391,8 @@ impl OpCodeHandler_Gv_M_as { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Gdq_Ev { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Gdq_Ev { @@ -1429,8 +1429,8 @@ impl OpCodeHandler_Gdq_Ev { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Gv_Ev3 { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Gv_Ev3 { @@ -1463,8 +1463,8 @@ impl OpCodeHandler_Gv_Ev3 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Gv_Ev2 { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Gv_Ev2 { @@ -1502,9 +1502,9 @@ impl OpCodeHandler_Gv_Ev2 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_R_C { has_modrm: bool, + base_reg: Register, code32: Code, code64: Code, - base_reg: Register, } impl OpCodeHandler_R_C { @@ -1556,9 +1556,9 @@ impl OpCodeHandler_R_C { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_C_R { has_modrm: bool, + base_reg: Register, code32: Code, code64: Code, - base_reg: Register, } impl OpCodeHandler_C_R { @@ -1851,10 +1851,10 @@ impl OpCodeHandler_Jdisp { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_PushOpSizeReg { has_modrm: bool, + reg: Register, code16: Code, code32: Code, code64: Code, - reg: Register, } impl OpCodeHandler_PushOpSizeReg { @@ -1941,8 +1941,8 @@ impl OpCodeHandler_PushEv { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ev_Gv { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Ev_Gv { @@ -1975,8 +1975,8 @@ impl OpCodeHandler_Ev_Gv { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ev_Gv_flags { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], state_flags_or_value: u32, } @@ -2058,8 +2058,8 @@ impl OpCodeHandler_Ev_Gv_32_64 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ev_Gv_Ib { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Ev_Gv_Ib { @@ -2094,8 +2094,8 @@ impl OpCodeHandler_Ev_Gv_Ib { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ev_Gv_CL { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Ev_Gv_CL { @@ -2167,8 +2167,8 @@ impl OpCodeHandler_Gv_Mp { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Gv_Eb { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Gv_Eb { @@ -2205,8 +2205,8 @@ impl OpCodeHandler_Gv_Eb { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Gv_Ew { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Gv_Ew { @@ -2392,8 +2392,8 @@ impl OpCodeHandler_Simple5_a32 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Simple5_ModRM_as { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Simple5_ModRM_as { @@ -2444,10 +2444,10 @@ impl OpCodeHandler_Simple4 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_PushSimpleReg { has_modrm: bool, - index: u32, code16: Code, code32: Code, code64: Code, + index: u32, } impl OpCodeHandler_PushSimpleReg { @@ -2483,8 +2483,8 @@ impl OpCodeHandler_PushSimpleReg { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_SimpleReg { has_modrm: bool, - index: u32, code: Code, + index: u32, } impl OpCodeHandler_SimpleReg { @@ -2878,8 +2878,8 @@ impl OpCodeHandler_RvMw_Gw { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Gv_Ev_Ib { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Gv_Ev_Ib { @@ -3004,8 +3004,8 @@ impl OpCodeHandler_Gv_Ev_32_64 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Gv_Ev_Iz { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Gv_Ev_Iz { @@ -3048,8 +3048,8 @@ impl OpCodeHandler_Gv_Ev_Iz { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Yb_Reg { has_modrm: bool, - code: Code, reg: Register, + code: Code, } impl OpCodeHandler_Yb_Reg { @@ -3144,8 +3144,8 @@ impl OpCodeHandler_Yv_Reg2 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Reg_Xb { has_modrm: bool, - code: Code, reg: Register, + code: Code, } impl OpCodeHandler_Reg_Xb { @@ -3240,8 +3240,8 @@ impl OpCodeHandler_Reg_Xv2 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Reg_Yb { has_modrm: bool, - code: Code, reg: Register, + code: Code, } impl OpCodeHandler_Reg_Yb { @@ -3423,8 +3423,8 @@ impl OpCodeHandler_Xv_Yv { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ev_Sw { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Ev_Sw { @@ -3487,8 +3487,8 @@ impl OpCodeHandler_M_Sw { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Gv_M { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Gv_M { @@ -3521,8 +3521,8 @@ impl OpCodeHandler_Gv_M { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Sw_Ev { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Sw_Ev { @@ -3620,8 +3620,8 @@ impl OpCodeHandler_Ap { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Reg_Ob { has_modrm: bool, - code: Code, reg: Register, + code: Code, } impl OpCodeHandler_Reg_Ob { @@ -3658,8 +3658,8 @@ impl OpCodeHandler_Reg_Ob { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Ob_Reg { has_modrm: bool, - code: Code, reg: Register, + code: Code, } impl OpCodeHandler_Ob_Reg { @@ -5521,8 +5521,8 @@ impl OpCodeHandler_VN { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Gv_Mv { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Gv_Mv { @@ -5555,8 +5555,8 @@ impl OpCodeHandler_Gv_Mv { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_Mv_Gv { has_modrm: bool, - reg_base: [u32; 3], code: [Code; 3], + reg_base: [u32; 3], } impl OpCodeHandler_Mv_Gv { diff --git a/src/rust/iced-x86/src/decoder/handlers/vex.rs b/src/rust/iced-x86/src/decoder/handlers/vex.rs index 051f728ca..c1ebcd918 100644 --- a/src/rust/iced-x86/src/decoder/handlers/vex.rs +++ b/src/rust/iced-x86/src/decoder/handlers/vex.rs @@ -74,9 +74,9 @@ impl OpCodeHandler_VEX_Simple { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VHEv { has_modrm: bool, + base_reg: Register, code_w0: Code, code_w1: Code, - base_reg: Register, } impl OpCodeHandler_VEX_VHEv { @@ -112,9 +112,9 @@ impl OpCodeHandler_VEX_VHEv { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VHEvIb { has_modrm: bool, + base_reg: Register, code_w0: Code, code_w1: Code, - base_reg: Register, } impl OpCodeHandler_VEX_VHEvIb { @@ -296,8 +296,8 @@ impl OpCodeHandler_VEX_WV { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VM { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_VEX_VM { @@ -328,8 +328,8 @@ impl OpCodeHandler_VEX_VM { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_MV { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_VEX_MV { @@ -423,8 +423,8 @@ impl OpCodeHandler_VEX_RdRq { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_rDI_VX_RX { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_VEX_rDI_VX_RX { @@ -535,9 +535,9 @@ impl OpCodeHandler_VEX_WVIb { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_Ed_V_Ib { has_modrm: bool, + base_reg: Register, code32: Code, code64: Code, - base_reg: Register, } impl OpCodeHandler_VEX_Ed_V_Ib { @@ -577,11 +577,11 @@ impl OpCodeHandler_VEX_Ed_V_Ib { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VHW { has_modrm: bool, - code_r: Code, - code_m: Code, base_reg1: Register, base_reg2: Register, base_reg3: Register, + code_r: Code, + code_m: Code, } impl OpCodeHandler_VEX_VHW { @@ -618,8 +618,8 @@ impl OpCodeHandler_VEX_VHW { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VWH { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_VEX_VWH { @@ -648,8 +648,8 @@ impl OpCodeHandler_VEX_VWH { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_WHV { has_modrm: bool, - code_r: Code, base_reg: Register, + code_r: Code, } impl OpCodeHandler_VEX_WHV { @@ -673,8 +673,8 @@ impl OpCodeHandler_VEX_WHV { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VHM { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_VEX_VHM { @@ -703,8 +703,8 @@ impl OpCodeHandler_VEX_VHM { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_MHV { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_VEX_MHV { @@ -733,10 +733,10 @@ impl OpCodeHandler_VEX_MHV { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VHWIb { has_modrm: bool, - code: Code, base_reg1: Register, base_reg2: Register, base_reg3: Register, + code: Code, } impl OpCodeHandler_VEX_VHWIb { @@ -767,8 +767,8 @@ impl OpCodeHandler_VEX_VHWIb { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_HRIb { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_VEX_HRIb { @@ -796,8 +796,8 @@ impl OpCodeHandler_VEX_HRIb { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VHWIs4 { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_VEX_VHWIs4 { @@ -828,8 +828,8 @@ impl OpCodeHandler_VEX_VHWIs4 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VHIs4W { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_VEX_VHIs4W { @@ -860,8 +860,8 @@ impl OpCodeHandler_VEX_VHIs4W { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VHWIs5 { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_VEX_VHWIs5 { @@ -894,8 +894,8 @@ impl OpCodeHandler_VEX_VHWIs5 { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VHIs5W { has_modrm: bool, - code: Code, base_reg: Register, + code: Code, } impl OpCodeHandler_VEX_VHIs5W { @@ -1080,8 +1080,8 @@ impl OpCodeHandler_VEX_M_VK { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VK_R { has_modrm: bool, - code: Code, gpr: Register, + code: Code, } impl OpCodeHandler_VEX_VK_R { @@ -1110,8 +1110,8 @@ impl OpCodeHandler_VEX_VK_R { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_G_VK { has_modrm: bool, - code: Code, gpr: Register, + code: Code, } impl OpCodeHandler_VEX_G_VK { @@ -1140,9 +1140,9 @@ impl OpCodeHandler_VEX_G_VK { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_Gv_W { has_modrm: bool, + base_reg: Register, code_w0: Code, code_w1: Code, - base_reg: Register, } impl OpCodeHandler_VEX_Gv_W { @@ -1178,9 +1178,9 @@ impl OpCodeHandler_VEX_Gv_W { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_Gv_RX { has_modrm: bool, + base_reg: Register, code32: Code, code64: Code, - base_reg: Register, } impl OpCodeHandler_VEX_Gv_RX { @@ -1216,9 +1216,9 @@ impl OpCodeHandler_VEX_Gv_RX { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_Gv_GPR_Ib { has_modrm: bool, + base_reg: Register, code32: Code, code64: Code, - base_reg: Register, } impl OpCodeHandler_VEX_Gv_GPR_Ib { @@ -1256,10 +1256,10 @@ impl OpCodeHandler_VEX_Gv_GPR_Ib { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VX_VSIB_HX { has_modrm: bool, - code: Code, base_reg1: Register, vsib_index: Register, base_reg3: Register, + code: Code, } impl OpCodeHandler_VEX_VX_VSIB_HX { @@ -1440,9 +1440,9 @@ impl OpCodeHandler_VEX_Hv_Ed_Id { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_GvM_VX_Ib { has_modrm: bool, + base_reg: Register, code32: Code, code64: Code, - base_reg: Register, } impl OpCodeHandler_VEX_GvM_VX_Ib { @@ -1717,8 +1717,8 @@ impl OpCodeHandler_VEX_Gq_HK_RK { #[repr(C)] pub(in crate::decoder) struct OpCodeHandler_VEX_VK_R_Ib { has_modrm: bool, - code: Code, gpr: Register, + code: Code, } impl OpCodeHandler_VEX_VK_R_Ib { From e6d0ead8ad4142ecc17824c5c31fc48bfcb90c87 Mon Sep 17 00:00:00 2001 From: wtfsck Date: Sat, 12 Feb 2022 18:23:03 +0100 Subject: [PATCH 3/6] Inline `Instruction Decode()` --- src/csharp/Intel/Iced/Intel/Decoder.cs | 1 + 1 file changed, 1 insertion(+) diff --git a/src/csharp/Intel/Iced/Intel/Decoder.cs b/src/csharp/Intel/Iced/Intel/Decoder.cs index 7dc8df3cc..baa1b6ff7 100644 --- a/src/csharp/Intel/Iced/Intel/Decoder.cs +++ b/src/csharp/Intel/Iced/Intel/Decoder.cs @@ -317,6 +317,7 @@ internal struct State { /// See also /// /// + [MethodImpl(MethodImplOptions.AggressiveInlining)] public Instruction Decode() { Decode(out var instr); return instr; From 93289f6da66e13fb33178edc0c6feb00a1a9ee2c Mon Sep 17 00:00:00 2001 From: wtfsck Date: Sat, 12 Feb 2022 18:23:08 +0100 Subject: [PATCH 4/6] Clear the fields faster --- src/csharp/Intel/Iced/Intel/Decoder.cs | 222 ++++----- .../Intel/DecoderInternal/OpCodeHandlers.cs | 6 +- .../DecoderInternal/OpCodeHandlers_EVEX.cs | 266 +++++----- .../DecoderInternal/OpCodeHandlers_Legacy.cs | 468 +++++++++--------- .../DecoderInternal/OpCodeHandlers_MVEX.cs | 62 +-- .../DecoderInternal/OpCodeHandlers_VEX.cs | 204 ++++---- 6 files changed, 612 insertions(+), 616 deletions(-) diff --git a/src/csharp/Intel/Iced/Intel/Decoder.cs b/src/csharp/Intel/Iced/Intel/Decoder.cs index baa1b6ff7..8229a4183 100644 --- a/src/csharp/Intel/Iced/Intel/Decoder.cs +++ b/src/csharp/Intel/Iced/Intel/Decoder.cs @@ -94,8 +94,8 @@ public sealed class Decoder : IEnumerable { internal readonly OpSize defaultInvertedAddressSize; internal readonly bool is64bMode; - internal struct State { - public uint modrm, mod, reg, rm; + // The fields were moved to a new struct so the jitter can efficiently clear all of them at once in Decode(out) + internal struct ZState { public uint instructionLength; public uint extraRegisterBase; // R << 3 public uint extraIndexRegisterBase; // X << 3 @@ -103,6 +103,12 @@ internal struct State { public uint extraIndexRegisterBaseVSIB; public StateFlags flags; public MandatoryPrefixByte mandatoryPrefix; + // 0=ES/CS/SS/DS, 1=FS/GS + public byte segmentPrio; + } + internal struct State { + public uint modrm, mod, reg, rm; + public ZState zs; public uint vvvv;// V`vvvv. Not stored in inverted form. If 16/32-bit mode, bits [4:3] are cleared public uint vvvv_invalidCheck;// vvvv bits, even in 16/32-bit mode. public uint aaa; @@ -111,11 +117,9 @@ internal struct State { public uint vectorLength; public OpSize operandSize; public OpSize addressSize; - // 0=ES/CS/SS/DS, 1=FS/GS - public byte segmentPrio; - public readonly EncodingKind Encoding => (EncodingKind)(((uint)flags >> (int)StateFlags.EncodingShift) & (uint)StateFlags.EncodingMask); + public readonly EncodingKind Encoding => (EncodingKind)(((uint)zs.flags >> (int)StateFlags.EncodingShift) & (uint)StateFlags.EncodingMask); #if MVEX - public int Sss => ((int)flags >> (int)StateFlags.MvexSssShift) & (int)StateFlags.MvexSssMask; + public int Sss => ((int)zs.flags >> (int)StateFlags.MvexSssShift) & (int)StateFlags.MvexSssMask; #endif } @@ -274,17 +278,17 @@ internal struct State { [MethodImpl(MethodImplOptions.AggressiveInlining)] internal uint ReadByte() { - uint instrLen = state.instructionLength; + uint instrLen = state.zs.instructionLength; if (instrLen < IcedConstants.MaxInstructionLength) { uint b = (uint)reader.ReadByte(); Debug.Assert(b <= byte.MaxValue || b > int.MaxValue); if (b <= byte.MaxValue) { - state.instructionLength = instrLen + 1; + state.zs.instructionLength = instrLen + 1; return b; } - state.flags |= StateFlags.NoMoreBytes; + state.zs.flags |= StateFlags.NoMoreBytes; } - state.flags |= StateFlags.IsInvalid; + state.zs.flags |= StateFlags.IsInvalid; return 0; } @@ -302,9 +306,9 @@ internal struct State { public DecoderError LastError { get { // NoMoreBytes error has highest priority - if ((state.flags & StateFlags.NoMoreBytes) != 0) + if ((state.zs.flags & StateFlags.NoMoreBytes) != 0) return DecoderError.NoMoreBytes; - if ((state.flags & StateFlags.IsInvalid) != 0) + if ((state.zs.flags & StateFlags.IsInvalid) != 0) return DecoderError.InvalidInstruction; return DecoderError.None; } @@ -329,35 +333,27 @@ internal struct State { /// Decoded instruction public void Decode(out Instruction instruction) { instruction = default; - state.instructionLength = 0; - state.extraRegisterBase = 0; - state.extraIndexRegisterBase = 0; - state.extraBaseRegisterBase = 0; - state.extraIndexRegisterBaseVSIB = 0; - state.flags = 0; - state.mandatoryPrefix = 0; - state.segmentPrio = 0; - + state.zs = default; state.operandSize = defaultOperandSize; state.addressSize = defaultAddressSize; uint b = ReadByte(); if ((b & rexMask) == 0x40) { - var flags2 = state.flags | StateFlags.HasRex; + var flags2 = state.zs.flags | StateFlags.HasRex; if ((b & 8) != 0) { flags2 |= StateFlags.W; state.operandSize = OpSize.Size64; } - state.flags = flags2; - state.extraRegisterBase = (b & 4) << 1; - state.extraIndexRegisterBase = (b & 2) << 2; - state.extraBaseRegisterBase = (b & 1) << 3; + state.zs.flags = flags2; + state.zs.extraRegisterBase = (b & 4) << 1; + state.zs.extraIndexRegisterBase = (b & 2) << 2; + state.zs.extraBaseRegisterBase = (b & 1) << 3; b = ReadByte(); } DecodeTable(handlers_MAP0[b], ref instruction); instruction.InternalCodeSize = defaultCodeSize; - uint instrLen = state.instructionLength; + uint instrLen = state.zs.instructionLength; Debug.Assert(0 <= instrLen && instrLen <= IcedConstants.MaxInstructionLength);// Could be 0 if there were no bytes available instruction.Length = (int)instrLen; var ip = instructionPointer; @@ -365,18 +361,18 @@ internal struct State { instructionPointer = ip; instruction.NextIP = ip; - var flags = state.flags; + var flags = state.zs.flags; if ((flags & (StateFlags.IsInvalid | StateFlags.Lock | StateFlags.IpRel32 | StateFlags.IpRel64)) != 0) { var addr = instruction.MemoryDisplacement64 + ip; instruction.MemoryDisplacement64 = addr; // RIP rel ops are common, but invalid/lock bits are usually never set, so exit early if possible if ((flags & (StateFlags.IsInvalid | StateFlags.Lock | StateFlags.IpRel64)) == StateFlags.IpRel64) return; - if ((state.flags & StateFlags.IpRel64) == 0) { + if ((state.zs.flags & StateFlags.IpRel64) == 0) { // Undo what we did above instruction.MemoryDisplacement64 = addr - ip; } - if ((state.flags & StateFlags.IpRel32) != 0) + if ((state.zs.flags & StateFlags.IpRel32) != 0) instruction.MemoryDisplacement64 = (uint)instruction.MemoryDisplacement64 + (uint)ip; if ((flags & StateFlags.IsInvalid) != 0 || @@ -384,7 +380,7 @@ internal struct State { instruction = default; Static.Assert(Code.INVALID == 0 ? 0 : -1); //instruction.Code = Code.INVALID; - state.flags = flags | StateFlags.IsInvalid; + state.zs.flags = flags | StateFlags.IsInvalid; instruction.InternalCodeSize = defaultCodeSize; instruction.Length = (int)instrLen; @@ -395,14 +391,14 @@ internal struct State { [MethodImpl(MethodImplOptions.AggressiveInlining)] internal void ResetRexPrefixState() { - state.flags &= ~(StateFlags.HasRex | StateFlags.W); - if ((state.flags & StateFlags.Has66) == 0) + state.zs.flags &= ~(StateFlags.HasRex | StateFlags.W); + if ((state.zs.flags & StateFlags.Has66) == 0) state.operandSize = defaultOperandSize; else state.operandSize = defaultInvertedOperandSize; - state.extraRegisterBase = 0; - state.extraIndexRegisterBase = 0; - state.extraBaseRegisterBase = 0; + state.zs.extraRegisterBase = 0; + state.zs.extraIndexRegisterBase = 0; + state.zs.extraBaseRegisterBase = 0; } [MethodImpl(MethodImplOptions.AggressiveInlining)] @@ -412,9 +408,9 @@ internal struct State { } [MethodImpl(MethodImplOptions.AggressiveInlining)] - internal uint GetCurrentInstructionPointer32() => (uint)instructionPointer + state.instructionLength; + internal uint GetCurrentInstructionPointer32() => (uint)instructionPointer + state.zs.instructionLength; [MethodImpl(MethodImplOptions.AggressiveInlining)] - internal ulong GetCurrentInstructionPointer64() => instructionPointer + state.instructionLength; + internal ulong GetCurrentInstructionPointer64() => instructionPointer + state.zs.instructionLength; [MethodImpl(MethodImplOptions.AggressiveInlining)] internal void ClearMandatoryPrefix(ref Instruction instruction) { @@ -425,11 +421,11 @@ internal struct State { [MethodImpl(MethodImplOptions.AggressiveInlining)] internal void SetXacquireXrelease(ref Instruction instruction) { if (instruction.HasLockPrefix) { - if (state.mandatoryPrefix == MandatoryPrefixByte.PF2) { + if (state.zs.mandatoryPrefix == MandatoryPrefixByte.PF2) { ClearMandatoryPrefixF2(ref instruction); instruction.InternalSetHasXacquirePrefix(); } - else if (state.mandatoryPrefix == MandatoryPrefixByte.PF3) { + else if (state.zs.mandatoryPrefix == MandatoryPrefixByte.PF3) { ClearMandatoryPrefixF3(ref instruction); instruction.InternalSetHasXreleasePrefix(); } @@ -439,19 +435,19 @@ internal struct State { [MethodImpl(MethodImplOptions.AggressiveInlining)] internal void ClearMandatoryPrefixF3(ref Instruction instruction) { Debug.Assert(state.Encoding == EncodingKind.Legacy); - Debug.Assert(state.mandatoryPrefix == MandatoryPrefixByte.PF3); + Debug.Assert(state.zs.mandatoryPrefix == MandatoryPrefixByte.PF3); instruction.InternalClearHasRepePrefix(); } [MethodImpl(MethodImplOptions.AggressiveInlining)] internal void ClearMandatoryPrefixF2(ref Instruction instruction) { Debug.Assert(state.Encoding == EncodingKind.Legacy); - Debug.Assert(state.mandatoryPrefix == MandatoryPrefixByte.PF2); + Debug.Assert(state.zs.mandatoryPrefix == MandatoryPrefixByte.PF2); instruction.InternalClearHasRepnePrefix(); } [MethodImpl(MethodImplOptions.AggressiveInlining)] - internal void SetInvalidInstruction() => state.flags |= StateFlags.IsInvalid; + internal void SetInvalidInstruction() => state.zs.flags |= StateFlags.IsInvalid; [MethodImpl(MethodImplOptions.AggressiveInlining)] internal void DecodeTable(OpCodeHandler[] table, ref Instruction instruction) => DecodeTable(table[(int)ReadByte()], ref instruction); @@ -481,15 +477,15 @@ internal struct State { #if NO_VEX SetInvalidInstruction(); #else - if ((((uint)(state.flags & StateFlags.HasRex) | (uint)state.mandatoryPrefix) & invalidCheckMask) != 0) + if ((((uint)(state.zs.flags & StateFlags.HasRex) | (uint)state.zs.mandatoryPrefix) & invalidCheckMask) != 0) SetInvalidInstruction(); // Undo what Decode() did if it got a REX prefix - state.flags &= ~StateFlags.W; - state.extraIndexRegisterBase = 0; - state.extraBaseRegisterBase = 0; + state.zs.flags &= ~StateFlags.W; + state.zs.extraIndexRegisterBase = 0; + state.zs.extraBaseRegisterBase = 0; #if DEBUG - state.flags |= (StateFlags)((uint)EncodingKind.VEX << (int)StateFlags.EncodingShift); + state.zs.flags |= (StateFlags)((uint)EncodingKind.VEX << (int)StateFlags.EncodingShift); #endif uint b = state.modrm; @@ -501,10 +497,10 @@ internal struct State { Static.Assert((int)MandatoryPrefixByte.P66 == 1 ? 0 : -1); Static.Assert((int)MandatoryPrefixByte.PF3 == 2 ? 0 : -1); Static.Assert((int)MandatoryPrefixByte.PF2 == 3 ? 0 : -1); - state.mandatoryPrefix = (MandatoryPrefixByte)(b & 3); + state.zs.mandatoryPrefix = (MandatoryPrefixByte)(b & 3); b = ~b; - state.extraRegisterBase = (b >> 4) & 8; + state.zs.extraRegisterBase = (b >> 4) & 8; // Bit 6 can only be 1 if it's 16/32-bit mode, so we don't need to change the mask b = (b >> 3) & 0x0F; @@ -519,18 +515,18 @@ internal struct State { #if NO_VEX SetInvalidInstruction(); #else - if ((((uint)(state.flags & StateFlags.HasRex) | (uint)state.mandatoryPrefix) & invalidCheckMask) != 0) + if ((((uint)(state.zs.flags & StateFlags.HasRex) | (uint)state.zs.mandatoryPrefix) & invalidCheckMask) != 0) SetInvalidInstruction(); // Undo what Decode() did if it got a REX prefix - state.flags &= ~StateFlags.W; + state.zs.flags &= ~StateFlags.W; #if DEBUG - state.flags |= (StateFlags)((uint)EncodingKind.VEX << (int)StateFlags.EncodingShift); + state.zs.flags |= (StateFlags)((uint)EncodingKind.VEX << (int)StateFlags.EncodingShift); #endif uint b2 = ReadByte(); Static.Assert((int)StateFlags.W == 0x80 ? 0 : -1); - state.flags |= (StateFlags)(b2 & 0x80); + state.zs.flags |= (StateFlags)(b2 & 0x80); Static.Assert((int)VectorLength.L128 == 0 ? 0 : -1); Static.Assert((int)VectorLength.L256 == 1 ? 0 : -1); @@ -540,16 +536,16 @@ internal struct State { Static.Assert((int)MandatoryPrefixByte.P66 == 1 ? 0 : -1); Static.Assert((int)MandatoryPrefixByte.PF3 == 2 ? 0 : -1); Static.Assert((int)MandatoryPrefixByte.PF2 == 3 ? 0 : -1); - state.mandatoryPrefix = (MandatoryPrefixByte)(b2 & 3); + state.zs.mandatoryPrefix = (MandatoryPrefixByte)(b2 & 3); b2 = (~b2 >> 3) & 0x0F; state.vvvv_invalidCheck = b2; state.vvvv = b2 & reg15Mask; uint b1 = state.modrm; uint b1x = ~b1 & maskE0; - state.extraRegisterBase = (b1x >> 4) & 8; - state.extraIndexRegisterBase = (b1x >> 3) & 8; - state.extraBaseRegisterBase = (b1x >> 2) & 8; + state.zs.extraRegisterBase = (b1x >> 4) & 8; + state.zs.extraIndexRegisterBase = (b1x >> 3) & 8; + state.zs.extraBaseRegisterBase = (b1x >> 2) & 8; OpCodeHandler[] handlers; var b = ReadByte(); @@ -576,18 +572,18 @@ internal struct State { #if NO_XOP SetInvalidInstruction(); #else - if ((((uint)(state.flags & StateFlags.HasRex) | (uint)state.mandatoryPrefix) & invalidCheckMask) != 0) + if ((((uint)(state.zs.flags & StateFlags.HasRex) | (uint)state.zs.mandatoryPrefix) & invalidCheckMask) != 0) SetInvalidInstruction(); // Undo what Decode() did if it got a REX prefix - state.flags &= ~StateFlags.W; + state.zs.flags &= ~StateFlags.W; #if DEBUG - state.flags |= (StateFlags)((uint)EncodingKind.XOP << (int)StateFlags.EncodingShift); + state.zs.flags |= (StateFlags)((uint)EncodingKind.XOP << (int)StateFlags.EncodingShift); #endif uint b2 = ReadByte(); Static.Assert((int)StateFlags.W == 0x80 ? 0 : -1); - state.flags |= (StateFlags)(b2 & 0x80); + state.zs.flags |= (StateFlags)(b2 & 0x80); Static.Assert((int)VectorLength.L128 == 0 ? 0 : -1); Static.Assert((int)VectorLength.L256 == 1 ? 0 : -1); @@ -597,16 +593,16 @@ internal struct State { Static.Assert((int)MandatoryPrefixByte.P66 == 1 ? 0 : -1); Static.Assert((int)MandatoryPrefixByte.PF3 == 2 ? 0 : -1); Static.Assert((int)MandatoryPrefixByte.PF2 == 3 ? 0 : -1); - state.mandatoryPrefix = (MandatoryPrefixByte)(b2 & 3); + state.zs.mandatoryPrefix = (MandatoryPrefixByte)(b2 & 3); b2 = (~b2 >> 3) & 0x0F; state.vvvv_invalidCheck = b2; state.vvvv = b2 & reg15Mask; uint b1 = state.modrm; uint b1x = ~b1 & maskE0; - state.extraRegisterBase = (b1x >> 4) & 8; - state.extraIndexRegisterBase = (b1x >> 3) & 8; - state.extraBaseRegisterBase = (b1x >> 2) & 8; + state.zs.extraRegisterBase = (b1x >> 4) & 8; + state.zs.extraIndexRegisterBase = (b1x >> 3) & 8; + state.zs.extraBaseRegisterBase = (b1x >> 2) & 8; OpCodeHandler[] handlers; var b = ReadByte(); @@ -629,10 +625,10 @@ internal struct State { #if NO_EVEX && !MVEX SetInvalidInstruction(); #else - if ((((uint)(state.flags & StateFlags.HasRex) | (uint)state.mandatoryPrefix) & invalidCheckMask) != 0) + if ((((uint)(state.zs.flags & StateFlags.HasRex) | (uint)state.zs.mandatoryPrefix) & invalidCheckMask) != 0) SetInvalidInstruction(); // Undo what Decode() did if it got a REX prefix - state.flags &= ~StateFlags.W; + state.zs.flags &= ~StateFlags.W; uint p0 = state.modrm; uint p1 = ReadByte(); @@ -646,17 +642,17 @@ internal struct State { #else if ((p0 & 8) == 0) { #if DEBUG - state.flags |= (StateFlags)((uint)EncodingKind.EVEX << (int)StateFlags.EncodingShift); + state.zs.flags |= (StateFlags)((uint)EncodingKind.EVEX << (int)StateFlags.EncodingShift); #endif Static.Assert((int)MandatoryPrefixByte.None == 0 ? 0 : -1); Static.Assert((int)MandatoryPrefixByte.P66 == 1 ? 0 : -1); Static.Assert((int)MandatoryPrefixByte.PF3 == 2 ? 0 : -1); Static.Assert((int)MandatoryPrefixByte.PF2 == 3 ? 0 : -1); - state.mandatoryPrefix = (MandatoryPrefixByte)(p1 & 3); + state.zs.mandatoryPrefix = (MandatoryPrefixByte)(p1 & 3); Static.Assert((int)StateFlags.W == 0x80 ? 0 : -1); - state.flags |= (StateFlags)(p1 & 0x80); + state.zs.flags |= (StateFlags)(p1 & 0x80); uint aaa = p2 & 7; state.aaa = aaa; @@ -665,12 +661,12 @@ internal struct State { // invalid if aaa == 0 and if we check for invalid instructions (it's all 1s) if ((aaa ^ invalidCheckMask) == uint.MaxValue) SetInvalidInstruction(); - state.flags |= StateFlags.z; + state.zs.flags |= StateFlags.z; instruction.InternalSetZeroingMasking(); } Static.Assert((int)StateFlags.b == 0x10 ? 0 : -1); - state.flags |= (StateFlags)(p2 & 0x10); + state.zs.flags |= (StateFlags)(p2 & 0x10); Static.Assert((int)VectorLength.L128 == 0 ? 0 : -1); Static.Assert((int)VectorLength.L256 == 1 ? 0 : -1); @@ -681,23 +677,23 @@ internal struct State { p1 = (~p1 >> 3) & 0x0F; if (is64bMode) { uint tmp = (~p2 & 8) << 1; - state.extraIndexRegisterBaseVSIB = tmp; + state.zs.extraIndexRegisterBaseVSIB = tmp; tmp += p1; state.vvvv = tmp; state.vvvv_invalidCheck = tmp; uint p0x = ~p0; - state.extraRegisterBase = (p0x >> 4) & 8; - state.extraIndexRegisterBase = (p0x >> 3) & 8; + state.zs.extraRegisterBase = (p0x >> 4) & 8; + state.zs.extraIndexRegisterBase = (p0x >> 3) & 8; state.extraRegisterBaseEVEX = p0x & 0x10; p0x >>= 2; state.extraBaseRegisterBaseEVEX = p0x & 0x18; - state.extraBaseRegisterBase = p0x & 8; + state.zs.extraBaseRegisterBase = p0x & 8; } else { state.vvvv_invalidCheck = p1; state.vvvv = p1 & 0x07; Static.Assert((int)StateFlags.IsInvalid == 0x40 ? 0 : -1); - state.flags |= (StateFlags)((~p2 & 8) << 3); + state.zs.flags |= (StateFlags)((~p2 & 8) << 3); } OpCodeHandler[] handlers; @@ -719,7 +715,7 @@ internal struct State { state.rm = p4 & 7; // Invalid if LL=3 and no rc Static.Assert((uint)StateFlags.b > 3 ? 0 : -1); - if ((((uint)(state.flags & StateFlags.b) | state.vectorLength) & invalidCheckMask) == 3) + if ((((uint)(state.zs.flags & StateFlags.b) | state.vectorLength) & invalidCheckMask) == 3) SetInvalidInstruction(); handler.Decode(this, ref instruction); } @@ -735,17 +731,17 @@ internal struct State { SetInvalidInstruction(); else { #if DEBUG - state.flags |= (StateFlags)((uint)EncodingKind.MVEX << (int)StateFlags.EncodingShift); + state.zs.flags |= (StateFlags)((uint)EncodingKind.MVEX << (int)StateFlags.EncodingShift); #endif Static.Assert((int)MandatoryPrefixByte.None == 0 ? 0 : -1); Static.Assert((int)MandatoryPrefixByte.P66 == 1 ? 0 : -1); Static.Assert((int)MandatoryPrefixByte.PF3 == 2 ? 0 : -1); Static.Assert((int)MandatoryPrefixByte.PF2 == 3 ? 0 : -1); - state.mandatoryPrefix = (MandatoryPrefixByte)(p1 & 3); + state.zs.mandatoryPrefix = (MandatoryPrefixByte)(p1 & 3); Static.Assert((int)StateFlags.W == 0x80 ? 0 : -1); - state.flags |= (StateFlags)(p1 & 0x80); + state.zs.flags |= (StateFlags)(p1 & 0x80); uint aaa = p2 & 7; state.aaa = aaa; @@ -754,21 +750,21 @@ internal struct State { Static.Assert((int)StateFlags.MvexSssShift == 16 ? 0 : -1); Static.Assert((int)StateFlags.MvexSssMask == 7 ? 0 : -1); Static.Assert((int)StateFlags.MvexEH == 1 << ((int)StateFlags.MvexSssShift + 3) ? 0 : -1); - state.flags |= (StateFlags)((p2 & 0xF0) << ((int)StateFlags.MvexSssShift - 4)); + state.zs.flags |= (StateFlags)((p2 & 0xF0) << ((int)StateFlags.MvexSssShift - 4)); p1 = (~p1 >> 3) & 0x0F; uint tmp = (~p2 & 8) << 1; - state.extraIndexRegisterBaseVSIB = tmp; + state.zs.extraIndexRegisterBaseVSIB = tmp; tmp += p1; state.vvvv = tmp; state.vvvv_invalidCheck = tmp; uint p0x = ~p0; - state.extraRegisterBase = (p0x >> 4) & 8; - state.extraIndexRegisterBase = (p0x >> 3) & 8; + state.zs.extraRegisterBase = (p0x >> 4) & 8; + state.zs.extraIndexRegisterBase = (p0x >> 3) & 8; state.extraRegisterBaseEVEX = p0x & 0x10; p0x >>= 2; state.extraBaseRegisterBaseEVEX = p0x & 0x18; - state.extraBaseRegisterBase = p0x & 8; + state.zs.extraBaseRegisterBase = p0x & 8; OpCodeHandler[] handlers; switch ((int)(p0 & 0xF)) { @@ -904,7 +900,7 @@ internal struct State { case 0: if (state.rm == 6) { instruction.InternalSetMemoryDisplSize(2); - displIndex = state.instructionLength; + displIndex = state.zs.instructionLength; instruction.MemoryDisplacement64 = ReadUInt16(); baseReg = Register.None; Debug.Assert(indexReg == Register.None); @@ -913,7 +909,7 @@ internal struct State { case 1: instruction.InternalSetMemoryDisplSize(1); - displIndex = state.instructionLength; + displIndex = state.zs.instructionLength; if (tupleType == TupleType.N1) instruction.MemoryDisplacement64 = (ushort)(sbyte)ReadByte(); else @@ -923,7 +919,7 @@ internal struct State { default: Debug.Assert(state.mod == 2); instruction.InternalSetMemoryDisplSize(2); - displIndex = state.instructionLength; + displIndex = state.zs.instructionLength; instruction.MemoryDisplacement64 = ReadUInt16(); break; } @@ -946,7 +942,7 @@ internal struct State { break; } else if (state.rm == 5) { - displIndex = state.instructionLength; + displIndex = state.zs.instructionLength; if (state.addressSize == OpSize.Size64) { instruction.MemoryDisplacement64 = (ulong)(int)ReadUInt32(); instruction.InternalSetMemoryDisplSize(4); @@ -957,11 +953,11 @@ internal struct State { } if (is64bMode) { if (state.addressSize == OpSize.Size64) { - state.flags |= StateFlags.IpRel64; + state.zs.flags |= StateFlags.IpRel64; instruction.InternalMemoryBase = Register.RIP; } else { - state.flags |= StateFlags.IpRel32; + state.zs.flags |= StateFlags.IpRel32; instruction.InternalMemoryBase = Register.EIP; } } @@ -969,7 +965,7 @@ internal struct State { } else { Debug.Assert(0 <= state.rm && state.rm <= 7 && state.rm != 4 && state.rm != 5); - instruction.InternalMemoryBase = (int)(state.extraBaseRegisterBase + state.rm) + baseReg; + instruction.InternalMemoryBase = (int)(state.zs.extraBaseRegisterBase + state.rm) + baseReg; return false; } @@ -977,7 +973,7 @@ internal struct State { if (state.rm == 4) { sib = ReadByte(); displSizeScale = 1; - displIndex = state.instructionLength; + displIndex = state.zs.instructionLength; if (tupleType == TupleType.N1) displ = (uint)(sbyte)ReadByte(); else @@ -987,7 +983,7 @@ internal struct State { else { Debug.Assert(0 <= state.rm && state.rm <= 7 && state.rm != 4); instruction.InternalSetMemoryDisplSize(1); - displIndex = state.instructionLength; + displIndex = state.zs.instructionLength; if (state.addressSize == OpSize.Size64) { if (tupleType == TupleType.N1) instruction.MemoryDisplacement64 = (ulong)(sbyte)ReadByte(); @@ -1000,7 +996,7 @@ internal struct State { else instruction.MemoryDisplacement64 = GetDisp8N(tupleType) * (uint)(sbyte)ReadByte(); } - instruction.InternalMemoryBase = (int)(state.extraBaseRegisterBase + state.rm) + baseReg; + instruction.InternalMemoryBase = (int)(state.zs.extraBaseRegisterBase + state.rm) + baseReg; return false; } @@ -1009,13 +1005,13 @@ internal struct State { if (state.rm == 4) { sib = ReadByte(); displSizeScale = state.addressSize == OpSize.Size64 ? 4U : 3; - displIndex = state.instructionLength; + displIndex = state.zs.instructionLength; displ = ReadUInt32(); break; } else { Debug.Assert(0 <= state.rm && state.rm <= 7 && state.rm != 4); - displIndex = state.instructionLength; + displIndex = state.zs.instructionLength; if (state.addressSize == OpSize.Size64) { instruction.MemoryDisplacement64 = (ulong)(int)ReadUInt32(); instruction.InternalSetMemoryDisplSize(4); @@ -1024,12 +1020,12 @@ internal struct State { instruction.MemoryDisplacement64 = ReadUInt32(); instruction.InternalSetMemoryDisplSize(3); } - instruction.InternalMemoryBase = (int)(state.extraBaseRegisterBase + state.rm) + baseReg; + instruction.InternalMemoryBase = (int)(state.zs.extraBaseRegisterBase + state.rm) + baseReg; return false; } } - uint index = ((sib >> 3) & 7) + state.extraIndexRegisterBase; + uint index = ((sib >> 3) & 7) + state.zs.extraIndexRegisterBase; uint @base = sib & 7; instruction.InternalMemoryIndexScale = (int)(sib >> 6); @@ -1038,10 +1034,10 @@ internal struct State { instruction.InternalMemoryIndex = (int)index + indexReg; } else - instruction.InternalMemoryIndex = (int)(index + state.extraIndexRegisterBaseVSIB) + indexReg; + instruction.InternalMemoryIndex = (int)(index + state.zs.extraIndexRegisterBaseVSIB) + indexReg; if (@base == 5 && state.mod == 0) { - displIndex = state.instructionLength; + displIndex = state.zs.instructionLength; if (state.addressSize == OpSize.Size64) { instruction.MemoryDisplacement64 = (ulong)(int)ReadUInt32(); instruction.InternalSetMemoryDisplSize(4); @@ -1052,7 +1048,7 @@ internal struct State { } } else { - instruction.InternalMemoryBase = (int)(@base + state.extraBaseRegisterBase) + baseReg; + instruction.InternalMemoryBase = (int)(@base + state.zs.extraBaseRegisterBase) + baseReg; instruction.InternalSetMemoryDisplSize(displSizeScale); if (state.addressSize == OpSize.Size64) instruction.MemoryDisplacement64 = (ulong)(int)displ; @@ -1064,7 +1060,7 @@ internal struct State { [MethodImpl(MethodImplOptions.AggressiveInlining)] uint GetDisp8N(TupleType tupleType) => - TupleTypeTable.GetDisp8N(tupleType, (state.flags & StateFlags.b) != 0); + TupleTypeTable.GetDisp8N(tupleType, (state.zs.flags & StateFlags.b) != 0); /// /// Gets the offsets of the constants (memory displacement and immediate) in the decoded instruction. @@ -1078,13 +1074,13 @@ internal struct State { int displSize = instruction.MemoryDisplSize; if (displSize != 0) { constantOffsets.DisplacementOffset = (byte)displIndex; - if (displSize == 8 && (state.flags & StateFlags.Addr64) == 0) + if (displSize == 8 && (state.zs.flags & StateFlags.Addr64) == 0) constantOffsets.DisplacementSize = 4; else constantOffsets.DisplacementSize = (byte)displSize; } - if ((state.flags & StateFlags.NoImm) == 0) { + if ((state.zs.flags & StateFlags.NoImm) == 0) { int extraImmSub = 0; for (int i = instruction.OpCount - 1; i >= 0; i--) { switch (instruction.GetOpKind(i)) { @@ -1119,16 +1115,16 @@ internal struct State { break; case OpKind.NearBranch16: - if ((state.flags & StateFlags.BranchImm8) != 0) { + if ((state.zs.flags & StateFlags.BranchImm8) != 0) { constantOffsets.ImmediateOffset = (byte)(instruction.Length - 1); constantOffsets.ImmediateSize = 1; } - else if ((state.flags & StateFlags.Xbegin) == 0) { + else if ((state.zs.flags & StateFlags.Xbegin) == 0) { constantOffsets.ImmediateOffset = (byte)(instruction.Length - 2); constantOffsets.ImmediateSize = 2; } else { - Debug.Assert((state.flags & StateFlags.Xbegin) != 0); + Debug.Assert((state.zs.flags & StateFlags.Xbegin) != 0); if (state.operandSize != OpSize.Size16) { constantOffsets.ImmediateOffset = (byte)(instruction.Length - 4); constantOffsets.ImmediateSize = 4; @@ -1142,16 +1138,16 @@ internal struct State { case OpKind.NearBranch32: case OpKind.NearBranch64: - if ((state.flags & StateFlags.BranchImm8) != 0) { + if ((state.zs.flags & StateFlags.BranchImm8) != 0) { constantOffsets.ImmediateOffset = (byte)(instruction.Length - 1); constantOffsets.ImmediateSize = 1; } - else if ((state.flags & StateFlags.Xbegin) == 0) { + else if ((state.zs.flags & StateFlags.Xbegin) == 0) { constantOffsets.ImmediateOffset = (byte)(instruction.Length - 4); constantOffsets.ImmediateSize = 4; } else { - Debug.Assert((state.flags & StateFlags.Xbegin) != 0); + Debug.Assert((state.zs.flags & StateFlags.Xbegin) != 0); if (state.operandSize != OpSize.Size16) { constantOffsets.ImmediateOffset = (byte)(instruction.Length - 4); constantOffsets.ImmediateSize = 4; diff --git a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers.cs b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers.cs index d558b3c9d..88356a059 100644 --- a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers.cs +++ b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers.cs @@ -132,7 +132,7 @@ public OpCodeHandler_MandatoryPrefix2(OpCodeHandler handler) decoder.state.Encoding == EncodingKind.EVEX || decoder.state.Encoding == EncodingKind.XOP || decoder.state.Encoding == EncodingKind.MVEX); - handlers[(int)decoder.state.mandatoryPrefix].Decode(decoder, ref instruction); + handlers[(int)decoder.state.zs.mandatoryPrefix].Decode(decoder, ref instruction); } } @@ -162,7 +162,7 @@ sealed class OpCodeHandler_MandatoryPrefix2_NoModRM : OpCodeHandler { decoder.state.Encoding == EncodingKind.EVEX || decoder.state.Encoding == EncodingKind.XOP || decoder.state.Encoding == EncodingKind.MVEX); - handlers[(int)decoder.state.mandatoryPrefix].Decode(decoder, ref instruction); + handlers[(int)decoder.state.zs.mandatoryPrefix].Decode(decoder, ref instruction); } } @@ -183,7 +183,7 @@ sealed class OpCodeHandler_W : OpCodeHandlerModRM { decoder.state.Encoding == EncodingKind.EVEX || decoder.state.Encoding == EncodingKind.XOP || decoder.state.Encoding == EncodingKind.MVEX); - ((decoder.state.flags & StateFlags.W) != 0 ? handlerW1 : handlerW0).Decode(decoder, ref instruction); + ((decoder.state.zs.flags & StateFlags.W) != 0 ? handlerW1 : handlerW0).Decode(decoder, ref instruction); } } diff --git a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_EVEX.cs b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_EVEX.cs index ef9ed516a..dede87511 100644 --- a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_EVEX.cs +++ b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_EVEX.cs @@ -53,7 +53,7 @@ sealed class OpCodeHandler_VectorLength_EVEX_er : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); int index = (int)decoder.state.vectorLength; - if (decoder.state.mod == 3 && (decoder.state.flags & StateFlags.b) != 0) + if (decoder.state.mod == 3 && (decoder.state.zs.flags & StateFlags.b) != 0) index = (int)VectorLength.L512; handlers[index].Decode(decoder, ref instruction); } @@ -76,11 +76,11 @@ sealed class OpCodeHandler_EVEX_V_H_Ev_er : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & StateFlags.z) | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & StateFlags.z) | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; TupleType tupleType; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(codeW1); tupleType = tupleTypeW1; gpr = Register.RAX; @@ -92,15 +92,15 @@ sealed class OpCodeHandler_EVEX_V_H_Ev_er : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; - if ((decoder.state.flags & StateFlags.b) != 0) { + instruction.Op2Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; + if ((decoder.state.zs.flags & StateFlags.b) != 0) { Static.Assert((int)RoundingControl.None == 0 ? 0 : -1); Static.Assert((int)RoundingControl.RoundToNearest == 1 ? 0 : -1); Static.Assert((int)RoundingControl.RoundDown == 2 ? 0 : -1); @@ -110,7 +110,7 @@ sealed class OpCodeHandler_EVEX_V_H_Ev_er : OpCodeHandlerModRM { } } else { - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.Op2Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction, tupleType); @@ -135,10 +135,10 @@ sealed class OpCodeHandler_EVEX_V_H_Ev_Ib : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(codeW1); gpr = Register.RAX; } @@ -148,18 +148,18 @@ sealed class OpCodeHandler_EVEX_V_H_Ev_Ib : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op2Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op2Kind = OpKind.Memory; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) decoder.ReadOpMem(ref instruction, tupleTypeW1); else decoder.ReadOpMem(ref instruction, tupleTypeW0); @@ -186,10 +186,10 @@ sealed class OpCodeHandler_EVEX_Ed_V_Ib : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -200,18 +200,18 @@ sealed class OpCodeHandler_EVEX_Ed_V_Ib : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op0Kind = OpKind.Memory; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) decoder.ReadOpMem(ref instruction, tupleType64); else decoder.ReadOpMem(ref instruction, tupleType32); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; instruction.Op2Kind = OpKind.Immediate8; instruction.InternalImmediate8 = decoder.ReadByte(); } @@ -238,7 +238,7 @@ sealed class OpCodeHandler_EVEX_VkHW_er : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; @@ -246,7 +246,7 @@ sealed class OpCodeHandler_EVEX_VkHW_er : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (onlySAE) instruction.InternalSetSuppressAllExceptions(); else { @@ -261,7 +261,7 @@ sealed class OpCodeHandler_EVEX_VkHW_er : OpCodeHandlerModRM { } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) @@ -291,7 +291,7 @@ sealed class OpCodeHandler_EVEX_VkHW_er_ur : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - int regNum0 = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX); + int regNum0 = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX); instruction.Op0Register = regNum0 + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; @@ -303,7 +303,7 @@ sealed class OpCodeHandler_EVEX_VkHW_er_ur : OpCodeHandlerModRM { instruction.Op2Register = regNum2 + baseReg; if (decoder.invalidCheckMask != 0 && (regNum0 == (int)decoder.state.vvvv || regNum0 == regNum2)) decoder.SetInvalidInstruction(); - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { Static.Assert((int)RoundingControl.None == 0 ? 0 : -1); Static.Assert((int)RoundingControl.RoundToNearest == 1 ? 0 : -1); Static.Assert((int)RoundingControl.RoundDown == 2 ? 0 : -1); @@ -316,7 +316,7 @@ sealed class OpCodeHandler_EVEX_VkHW_er_ur : OpCodeHandlerModRM { if (decoder.invalidCheckMask != 0 && regNum0 == (int)decoder.state.vvvv) decoder.SetInvalidInstruction(); instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) @@ -370,12 +370,12 @@ sealed class OpCodeHandler_EVEX_VkW_er : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg2; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (onlySAE) instruction.InternalSetSuppressAllExceptions(); else { @@ -390,7 +390,7 @@ sealed class OpCodeHandler_EVEX_VkW_er : OpCodeHandlerModRM { } else { instruction.Op1Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) @@ -422,17 +422,17 @@ sealed class OpCodeHandler_EVEX_VkWIb_er : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg2; - if ((decoder.state.flags & StateFlags.b) != 0) + if ((decoder.state.zs.flags & StateFlags.b) != 0) instruction.InternalSetSuppressAllExceptions(); } else { instruction.Op1Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) + if ((decoder.state.zs.flags & StateFlags.b) != 0) instruction.InternalSetIsBroadcast(); decoder.ReadOpMem(ref instruction, tupleType); } @@ -472,17 +472,17 @@ sealed class OpCodeHandler_EVEX_VkW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg2; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { instruction.Op1Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) @@ -526,14 +526,14 @@ sealed class OpCodeHandler_EVEX_WkV : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & StateFlags.b) | decoder.state.vvvv_invalidCheck) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & StateFlags.b) | decoder.state.vvvv_invalidCheck) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg2; - if (((uint)(decoder.state.flags & StateFlags.z) & disallowZeroingMasking & decoder.invalidCheckMask) != 0) + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg2; + if (((uint)(decoder.state.zs.flags & StateFlags.z) & disallowZeroingMasking & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -542,7 +542,7 @@ sealed class OpCodeHandler_EVEX_WkV : OpCodeHandlerModRM { } else { instruction.Op0Kind = OpKind.Memory; - if (((uint)(decoder.state.flags & StateFlags.z) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.z) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); decoder.ReadOpMem(ref instruction, tupleType); } @@ -562,13 +562,13 @@ sealed class OpCodeHandler_EVEX_VkM : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & StateFlags.b) | decoder.state.vvvv_invalidCheck) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & StateFlags.b) | decoder.state.vvvv_invalidCheck) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { @@ -601,17 +601,17 @@ sealed class OpCodeHandler_EVEX_VkWIb : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg2; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { instruction.Op1Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) @@ -639,7 +639,7 @@ sealed class OpCodeHandler_EVEX_WkVIb : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & StateFlags.b) | decoder.state.vvvv_invalidCheck) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & StateFlags.b) | decoder.state.vvvv_invalidCheck) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); @@ -650,13 +650,13 @@ sealed class OpCodeHandler_EVEX_WkVIb : OpCodeHandlerModRM { } else { instruction.Op0Kind = OpKind.Memory; - if (((uint)(decoder.state.flags & StateFlags.z) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.z) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); decoder.ReadOpMem(ref instruction, tupleType); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg2; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg2; instruction.Op2Kind = OpKind.Immediate8; instruction.InternalImmediate8 = decoder.ReadByte(); } @@ -688,12 +688,12 @@ sealed class OpCodeHandler_EVEX_HkWIb : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg2; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { instruction.Op1Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) @@ -722,7 +722,7 @@ sealed class OpCodeHandler_EVEX_HWIb : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); instruction.InternalSetCodeNoCheck(code); - if ((((uint)(decoder.state.flags & (StateFlags.z | StateFlags.b)) | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.z | StateFlags.b)) | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -732,7 +732,7 @@ sealed class OpCodeHandler_EVEX_HWIb : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg2; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { @@ -767,18 +767,18 @@ sealed class OpCodeHandler_EVEX_WkVIb_er : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg1; - if ((decoder.state.flags & StateFlags.b) != 0) + if ((decoder.state.zs.flags & StateFlags.b) != 0) instruction.InternalSetSuppressAllExceptions(); } else { instruction.Op0Kind = OpKind.Memory; - if (((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); decoder.ReadOpMem(ref instruction, tupleType); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg2; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg2; instruction.Op2Kind = OpKind.Immediate8; instruction.InternalImmediate8 = decoder.ReadByte(); } @@ -803,19 +803,19 @@ sealed class OpCodeHandler_EVEX_VW_er : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; - if ((((uint)(decoder.state.flags & StateFlags.z) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; + if ((((uint)(decoder.state.zs.flags & StateFlags.z) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg2; - if ((decoder.state.flags & StateFlags.b) != 0) + if ((decoder.state.zs.flags & StateFlags.b) != 0) instruction.InternalSetSuppressAllExceptions(); } else { instruction.Op1Kind = OpKind.Memory; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); decoder.ReadOpMem(ref instruction, tupleType); } @@ -837,18 +837,18 @@ sealed class OpCodeHandler_EVEX_VW : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.z | StateFlags.b)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.z | StateFlags.b)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg2; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { @@ -873,18 +873,18 @@ sealed class OpCodeHandler_EVEX_WV : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.z | StateFlags.b)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.z | StateFlags.b)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg2; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { @@ -907,13 +907,13 @@ sealed class OpCodeHandler_EVEX_VM : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.z | StateFlags.b)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.z | StateFlags.b)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { @@ -934,13 +934,13 @@ sealed class OpCodeHandler_EVEX_VK : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; @@ -962,7 +962,7 @@ sealed class OpCodeHandler_EVEX_KR : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa | decoder.state.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa | decoder.state.zs.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); @@ -994,7 +994,7 @@ sealed class OpCodeHandler_EVEX_KkHWIb_sae : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & StateFlags.z) | decoder.state.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & StateFlags.z) | decoder.state.zs.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); @@ -1008,12 +1008,12 @@ sealed class OpCodeHandler_EVEX_KkHWIb_sae : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg; - if ((decoder.state.flags & StateFlags.b) != 0) + if ((decoder.state.zs.flags & StateFlags.b) != 0) instruction.InternalSetSuppressAllExceptions(); } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) @@ -1058,7 +1058,7 @@ sealed class OpCodeHandler_EVEX_VkHW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg2; @@ -1066,12 +1066,12 @@ sealed class OpCodeHandler_EVEX_VkHW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg3; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) @@ -1101,7 +1101,7 @@ sealed class OpCodeHandler_EVEX_VkHM : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg2; @@ -1109,7 +1109,7 @@ sealed class OpCodeHandler_EVEX_VkHM : OpCodeHandlerModRM { decoder.SetInvalidInstruction(); else { instruction.Op2Kind = OpKind.Memory; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); decoder.ReadOpMem(ref instruction, tupleType); } @@ -1148,7 +1148,7 @@ sealed class OpCodeHandler_EVEX_VkHWIb : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg2; @@ -1156,12 +1156,12 @@ sealed class OpCodeHandler_EVEX_VkHWIb : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg3; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) @@ -1197,7 +1197,7 @@ sealed class OpCodeHandler_EVEX_VkHWIb_er : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg2; @@ -1205,12 +1205,12 @@ sealed class OpCodeHandler_EVEX_VkHWIb_er : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg3; - if ((decoder.state.flags & StateFlags.b) != 0) + if ((decoder.state.zs.flags & StateFlags.b) != 0) instruction.InternalSetSuppressAllExceptions(); } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) @@ -1246,18 +1246,18 @@ sealed class OpCodeHandler_EVEX_KkHW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; - if ((((uint)(decoder.state.flags & StateFlags.z) | decoder.state.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & StateFlags.z) | decoder.state.zs.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) @@ -1289,18 +1289,18 @@ sealed class OpCodeHandler_EVEX_KP1HW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; - if ((((uint)(decoder.state.flags & StateFlags.z) | decoder.state.aaa | decoder.state.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & StateFlags.z) | decoder.state.aaa | decoder.state.zs.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) + if ((decoder.state.zs.flags & StateFlags.b) != 0) instruction.InternalSetIsBroadcast(); decoder.ReadOpMem(ref instruction, tupleType); } @@ -1330,18 +1330,18 @@ sealed class OpCodeHandler_EVEX_KkHWIb : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; - if ((((uint)(decoder.state.flags & StateFlags.z) | decoder.state.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & StateFlags.z) | decoder.state.zs.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) @@ -1371,14 +1371,14 @@ sealed class OpCodeHandler_EVEX_WkHV : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op2Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; } } @@ -1395,13 +1395,13 @@ sealed class OpCodeHandler_EVEX_VHWIb : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; @@ -1447,12 +1447,12 @@ sealed class OpCodeHandler_EVEX_VHW : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg1; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg2; @@ -1483,13 +1483,13 @@ sealed class OpCodeHandler_EVEX_VHM : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; @@ -1519,25 +1519,25 @@ sealed class OpCodeHandler_EVEX_Gv_W_er : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & StateFlags.z) | decoder.state.vvvv_invalidCheck | decoder.state.aaa | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & StateFlags.z) | decoder.state.vvvv_invalidCheck | decoder.state.aaa | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(codeW1); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; } else { instruction.InternalSetCodeNoCheck(codeW0); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; } if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (onlySAE) instruction.InternalSetSuppressAllExceptions(); else { @@ -1551,7 +1551,7 @@ sealed class OpCodeHandler_EVEX_Gv_W_er : OpCodeHandlerModRM { } } else { - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.Op1Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction, tupleType); @@ -1574,11 +1574,11 @@ sealed class OpCodeHandler_EVEX_VX_Ev : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; TupleType tupleType; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); tupleType = tupleTypeW1; gpr = Register.RAX; @@ -1590,11 +1590,11 @@ sealed class OpCodeHandler_EVEX_VX_Ev : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.XMM0; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op1Kind = OpKind.Memory; @@ -1618,14 +1618,14 @@ sealed class OpCodeHandler_EVEX_Ev_VX : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.XMM0; Register gpr; TupleType tupleType; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); tupleType = tupleTypeW1; gpr = Register.RAX; @@ -1638,7 +1638,7 @@ sealed class OpCodeHandler_EVEX_Ev_VX : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op0Kind = OpKind.Memory; @@ -1660,10 +1660,10 @@ sealed class OpCodeHandler_EVEX_Ev_VX_Ib : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -1673,7 +1673,7 @@ sealed class OpCodeHandler_EVEX_Ev_VX_Ib : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + gpr; Debug.Assert(decoder.state.mod == 3); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; @@ -1696,13 +1696,13 @@ sealed class OpCodeHandler_EVEX_MV : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { @@ -1731,10 +1731,10 @@ sealed class OpCodeHandler_EVEX_VkEv_REXW : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & StateFlags.b) | decoder.state.vvvv_invalidCheck) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & StateFlags.b) | decoder.state.vvvv_invalidCheck) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { Debug.Assert(code64 != Code.INVALID); instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; @@ -1746,11 +1746,11 @@ sealed class OpCodeHandler_EVEX_VkEv_REXW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else decoder.SetInvalidInstruction(); @@ -1772,11 +1772,11 @@ sealed class OpCodeHandler_EVEX_Vk_VSIB : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if (decoder.invalidCheckMask != 0 && (((uint)(decoder.state.flags & (StateFlags.z | StateFlags.b)) | (decoder.state.vvvv_invalidCheck & 0xF)) != 0 || decoder.state.aaa == 0)) + if (decoder.invalidCheckMask != 0 && (((uint)(decoder.state.zs.flags & (StateFlags.z | StateFlags.b)) | (decoder.state.vvvv_invalidCheck & 0xF)) != 0 || decoder.state.aaa == 0)) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); - int regNum = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX); + int regNum = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; instruction.Op0Register = regNum + baseReg; @@ -1808,13 +1808,13 @@ sealed class OpCodeHandler_EVEX_VSIB_k1_VX : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if (decoder.invalidCheckMask != 0 && (((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | (decoder.state.vvvv_invalidCheck & 0xF)) != 0 || decoder.state.aaa == 0)) + if (decoder.invalidCheckMask != 0 && (((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | (decoder.state.vvvv_invalidCheck & 0xF)) != 0 || decoder.state.aaa == 0)) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { @@ -1837,7 +1837,7 @@ sealed class OpCodeHandler_EVEX_VSIB_k1 : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if (decoder.invalidCheckMask != 0 && (((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | (decoder.state.vvvv_invalidCheck & 0xF)) != 0 || decoder.state.aaa == 0)) + if (decoder.invalidCheckMask != 0 && (((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | (decoder.state.vvvv_invalidCheck & 0xF)) != 0 || decoder.state.aaa == 0)) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); @@ -1867,10 +1867,10 @@ sealed class OpCodeHandler_EVEX_GvM_VX_Ib : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & (StateFlags.b | StateFlags.z)) | decoder.state.vvvv_invalidCheck | decoder.state.aaa) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -1881,18 +1881,18 @@ sealed class OpCodeHandler_EVEX_GvM_VX_Ib : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op0Kind = OpKind.Memory; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) decoder.ReadOpMem(ref instruction, tupleType64); else decoder.ReadOpMem(ref instruction, tupleType32); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + baseReg; instruction.Op2Kind = OpKind.Immediate8; instruction.InternalImmediate8 = decoder.ReadByte(); } @@ -1913,7 +1913,7 @@ sealed class OpCodeHandler_EVEX_KkWIb : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.EVEX); - if ((((uint)(decoder.state.flags & StateFlags.z) | decoder.state.vvvv_invalidCheck | decoder.state.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) + if ((((uint)(decoder.state.zs.flags & StateFlags.z) | decoder.state.vvvv_invalidCheck | decoder.state.zs.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); @@ -1924,12 +1924,12 @@ sealed class OpCodeHandler_EVEX_KkWIb : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + baseReg; - if (((uint)(decoder.state.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) + if (((uint)(decoder.state.zs.flags & StateFlags.b) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { instruction.Op1Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.b) != 0) { + if ((decoder.state.zs.flags & StateFlags.b) != 0) { if (canBroadcast) instruction.InternalSetIsBroadcast(); else if (decoder.invalidCheckMask != 0) diff --git a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs index 99ca9f98e..cd218ab84 100644 --- a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs +++ b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs @@ -87,7 +87,7 @@ sealed class OpCodeHandler_PrefixEsCsSsDs : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if (!decoder.is64bMode || decoder.state.segmentPrio <= 0) + if (!decoder.is64bMode || decoder.state.zs.segmentPrio <= 0) instruction.SegmentPrefix = seg; decoder.ResetRexPrefixState(); @@ -107,7 +107,7 @@ sealed class OpCodeHandler_PrefixFsGs : OpCodeHandler { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); instruction.SegmentPrefix = seg; - decoder.state.segmentPrio = 1; + decoder.state.zs.segmentPrio = 1; decoder.ResetRexPrefixState(); decoder.CallOpCodeHandlerXXTable(ref instruction); @@ -120,10 +120,10 @@ sealed class OpCodeHandler_Prefix66 : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - decoder.state.flags |= StateFlags.Has66; + decoder.state.zs.flags |= StateFlags.Has66; decoder.state.operandSize = decoder.defaultInvertedOperandSize; - if (decoder.state.mandatoryPrefix == MandatoryPrefixByte.None) - decoder.state.mandatoryPrefix = MandatoryPrefixByte.P66; + if (decoder.state.zs.mandatoryPrefix == MandatoryPrefixByte.None) + decoder.state.zs.mandatoryPrefix = MandatoryPrefixByte.P66; decoder.ResetRexPrefixState(); decoder.CallOpCodeHandlerXXTable(ref instruction); @@ -150,7 +150,7 @@ sealed class OpCodeHandler_PrefixF0 : OpCodeHandler { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); instruction.InternalSetHasLockPrefix(); - decoder.state.flags |= StateFlags.Lock; + decoder.state.zs.flags |= StateFlags.Lock; decoder.ResetRexPrefixState(); decoder.CallOpCodeHandlerXXTable(ref instruction); @@ -164,7 +164,7 @@ sealed class OpCodeHandler_PrefixF2 : OpCodeHandler { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); instruction.InternalSetHasRepnePrefix(); - decoder.state.mandatoryPrefix = MandatoryPrefixByte.PF2; + decoder.state.zs.mandatoryPrefix = MandatoryPrefixByte.PF2; decoder.ResetRexPrefixState(); decoder.CallOpCodeHandlerXXTable(ref instruction); @@ -178,7 +178,7 @@ sealed class OpCodeHandler_PrefixF3 : OpCodeHandler { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); instruction.InternalSetHasRepePrefix(); - decoder.state.mandatoryPrefix = MandatoryPrefixByte.PF3; + decoder.state.zs.mandatoryPrefix = MandatoryPrefixByte.PF3; decoder.ResetRexPrefixState(); decoder.CallOpCodeHandlerXXTable(ref instruction); @@ -201,19 +201,19 @@ sealed class OpCodeHandler_PrefixREX : OpCodeHandler { if (decoder.is64bMode) { if ((rex & 8) != 0) { decoder.state.operandSize = OpSize.Size64; - decoder.state.flags |= StateFlags.HasRex | StateFlags.W; + decoder.state.zs.flags |= StateFlags.HasRex | StateFlags.W; } else { - decoder.state.flags |= StateFlags.HasRex; - decoder.state.flags &= ~StateFlags.W; - if ((decoder.state.flags & StateFlags.Has66) == 0) + decoder.state.zs.flags |= StateFlags.HasRex; + decoder.state.zs.flags &= ~StateFlags.W; + if ((decoder.state.zs.flags & StateFlags.Has66) == 0) decoder.state.operandSize = OpSize.Size32; else decoder.state.operandSize = OpSize.Size16; } - decoder.state.extraRegisterBase = (rex & 4) << 1; - decoder.state.extraIndexRegisterBase = (rex & 2) << 2; - decoder.state.extraBaseRegisterBase = (rex & 1) << 3; + decoder.state.zs.extraRegisterBase = (rex & 4) << 1; + decoder.state.zs.extraIndexRegisterBase = (rex & 2) << 2; + decoder.state.zs.extraBaseRegisterBase = (rex & 1) << 3; decoder.CallOpCodeHandlerXXTable(ref instruction); } @@ -363,7 +363,7 @@ sealed class OpCodeHandler_MandatoryPrefix : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); decoder.ClearMandatoryPrefix(ref instruction); - handlers[(int)decoder.state.mandatoryPrefix].Decode(decoder, ref instruction); + handlers[(int)decoder.state.zs.mandatoryPrefix].Decode(decoder, ref instruction); } } @@ -410,7 +410,7 @@ sealed class OpCodeHandler_MandatoryPrefix3 : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); var handlers = decoder.state.mod == 3 ? handlers_reg : handlers_mem; - var info = handlers[(int)decoder.state.mandatoryPrefix]; + var info = handlers[(int)decoder.state.zs.mandatoryPrefix]; if (info.mandatoryPrefix) decoder.ClearMandatoryPrefix(ref instruction); info.handler.Decode(decoder, ref instruction); @@ -435,7 +435,7 @@ sealed class OpCodeHandler_MandatoryPrefix4 : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); OpCodeHandler handler; - var prefix = decoder.state.mandatoryPrefix; + var prefix = decoder.state.zs.mandatoryPrefix; switch (prefix) { case MandatoryPrefixByte.None: handler = handlerNP; @@ -485,7 +485,7 @@ sealed class OpCodeHandler_MandatoryPrefix_NoModRM : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); decoder.ClearMandatoryPrefix(ref instruction); - handlers[(int)decoder.state.mandatoryPrefix].Decode(decoder, ref instruction); + handlers[(int)decoder.state.zs.mandatoryPrefix].Decode(decoder, ref instruction); } } @@ -543,14 +543,14 @@ sealed class OpCodeHandler_Ev_Iz : OpCodeHandlerModRM { if (decoder.state.mod < 3) { Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); Static.Assert((int)StateFlags.AllowLock == 0x00002000 ? 0 : -1); - decoder.state.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); + decoder.state.zs.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); instruction.Op0Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction); } else { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } if ((uint)operandSize == (uint)OpSize.Size32) { instruction.Op1Kind = OpKind.Immediate32; @@ -586,12 +586,12 @@ sealed class OpCodeHandler_Ev_Ib : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); Static.Assert((int)StateFlags.AllowLock == 0x00002000 ? 0 : -1); - decoder.state.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); + decoder.state.zs.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); instruction.Op0Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction); } @@ -624,12 +624,12 @@ sealed class OpCodeHandler_Ev_Ib2 : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); Static.Assert((int)StateFlags.AllowLock == 0x00002000 ? 0 : -1); - decoder.state.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); + decoder.state.zs.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); instruction.Op0Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction); } @@ -650,11 +650,11 @@ sealed class OpCodeHandler_Ev_1 : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } instruction.Op1Kind = OpKind.Immediate8; instruction.InternalImmediate8 = 1; - decoder.state.flags |= StateFlags.NoImm; + decoder.state.zs.flags |= StateFlags.NoImm; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -679,7 +679,7 @@ sealed class OpCodeHandler_Ev_CL : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -707,12 +707,12 @@ sealed class OpCodeHandler_Ev : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); Static.Assert((int)StateFlags.AllowLock == 0x00002000 ? 0 : -1); - decoder.state.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); + decoder.state.zs.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); instruction.Op0Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction); } @@ -731,7 +731,7 @@ sealed class OpCodeHandler_Rv : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; Debug.Assert(decoder.state.mod == 3); } } @@ -759,7 +759,7 @@ sealed class OpCodeHandler_Rv_32_64 : OpCodeHandlerModRM { Debug.Assert(decoder.state.mod == 3); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } } @@ -775,7 +775,7 @@ sealed class OpCodeHandler_Rq : OpCodeHandlerModRM { Debug.Assert(decoder.state.mod == 3); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.RAX; } } @@ -796,20 +796,20 @@ sealed class OpCodeHandler_Ev_REXW : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) + if ((decoder.state.zs.flags & StateFlags.W) != 0) instruction.InternalSetCodeNoCheck(code64); else instruction.InternalSetCodeNoCheck(code32); Static.Assert((uint)StateFlags.Has66 != 4 ? 0 : -1); - if ((((flags & 4) | (uint)(decoder.state.flags & StateFlags.Has66)) & decoder.invalidCheckMask) == (4 | (uint)StateFlags.Has66)) + if ((((flags & 4) | (uint)(decoder.state.zs.flags & StateFlags.Has66)) & decoder.invalidCheckMask) == (4 | (uint)StateFlags.Has66)) decoder.SetInvalidInstruction(); if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - if ((decoder.state.flags & StateFlags.W) != 0) - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.RAX; + if ((decoder.state.zs.flags & StateFlags.W) != 0) + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.RAX; else - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.EAX; if ((disallowReg & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } @@ -848,9 +848,9 @@ sealed class OpCodeHandler_Evj : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; if ((decoder.options & DecoderOptions.AMD) == 0 || decoder.state.operandSize != OpSize.Size16) - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.RAX; else - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } } else { @@ -915,7 +915,7 @@ sealed class OpCodeHandler_Evw : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -937,7 +937,7 @@ sealed class OpCodeHandler_Ew : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -983,7 +983,7 @@ sealed class OpCodeHandler_Gv_Ev : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod < 3) { instruction.Op1Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction); @@ -991,7 +991,7 @@ sealed class OpCodeHandler_Gv_Ev : OpCodeHandlerModRM { else { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } } } @@ -1006,11 +1006,11 @@ sealed class OpCodeHandler_Gd_Rd : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.EAX; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.EAX; } else decoder.SetInvalidInstruction(); @@ -1029,7 +1029,7 @@ sealed class OpCodeHandler_Gv_M_as : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[addressSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)addressSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op0Register = ((int)addressSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { @@ -1052,13 +1052,13 @@ sealed class OpCodeHandler_Gdq_Ev : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; if ((uint)operandSize != (uint)OpSize.Size64) - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; else - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op1Kind = OpKind.Memory; @@ -1079,11 +1079,11 @@ sealed class OpCodeHandler_Gv_Ev3 : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op1Kind = OpKind.Memory; @@ -1104,11 +1104,11 @@ sealed class OpCodeHandler_Gv_Ev2 : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; + uint index = decoder.state.rm + decoder.state.zs.extraBaseRegisterBase; if (decoder.state.operandSize != OpSize.Size16) instruction.Op1Register = (int)index + Register.EAX; else @@ -1138,22 +1138,22 @@ sealed class OpCodeHandler_R_C : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code64); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.RAX; } else { instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.EAX; } - var extraRegisterBase = decoder.state.extraRegisterBase; + var extraRegisterBase = decoder.state.zs.extraRegisterBase; // LOCK MOV CR0 is supported by some AMD CPUs if (baseReg == Register.CR0 && instruction.HasLockPrefix && (decoder.options & DecoderOptions.AMD) != 0) { if ((extraRegisterBase & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); extraRegisterBase = 8; instruction.InternalClearHasLockPrefix(); - decoder.state.flags &= ~StateFlags.Lock; + decoder.state.zs.flags &= ~StateFlags.Lock; } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; @@ -1193,22 +1193,22 @@ sealed class OpCodeHandler_C_R : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code64); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.RAX; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.RAX; } else { instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.EAX; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.EAX; } - var extraRegisterBase = decoder.state.extraRegisterBase; + var extraRegisterBase = decoder.state.zs.extraRegisterBase; // LOCK MOV CR0 is supported by some AMD CPUs if (baseReg == Register.CR0 && instruction.HasLockPrefix && (decoder.options & DecoderOptions.AMD) != 0) { if ((extraRegisterBase & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); extraRegisterBase = 8; instruction.InternalClearHasLockPrefix(); - decoder.state.flags &= ~StateFlags.Lock; + decoder.state.zs.flags &= ~StateFlags.Lock; } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; @@ -1244,7 +1244,7 @@ sealed class OpCodeHandler_Jb : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - decoder.state.flags |= StateFlags.BranchImm8; + decoder.state.zs.flags |= StateFlags.BranchImm8; if (decoder.is64bMode) { if ((decoder.options & DecoderOptions.AMD) == 0 || decoder.state.operandSize != OpSize.Size16) { instruction.InternalSetCodeNoCheck(code64); @@ -1285,7 +1285,7 @@ sealed class OpCodeHandler_Jx : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - decoder.state.flags |= StateFlags.Xbegin; + decoder.state.zs.flags |= StateFlags.Xbegin; if (decoder.is64bMode) { if (decoder.state.operandSize == OpSize.Size32) { instruction.InternalSetCodeNoCheck(code32); @@ -1381,7 +1381,7 @@ sealed class OpCodeHandler_Jb2 : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - decoder.state.flags |= StateFlags.BranchImm8; + decoder.state.zs.flags |= StateFlags.BranchImm8; if (decoder.is64bMode) { if ((decoder.options & DecoderOptions.AMD) == 0 || decoder.state.operandSize != OpSize.Size16) { if (decoder.state.addressSize == OpSize.Size64) @@ -1507,7 +1507,7 @@ sealed class OpCodeHandler_PushEv : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; + uint index = decoder.state.rm + decoder.state.zs.extraBaseRegisterBase; if (decoder.is64bMode) { if (decoder.state.operandSize != OpSize.Size16) instruction.Op0Register = (int)index + Register.RAX; @@ -1546,16 +1546,16 @@ sealed class OpCodeHandler_Ev_Gv : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); Static.Assert((int)StateFlags.AllowLock == 0x00002000 ? 0 : -1); - decoder.state.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); + decoder.state.zs.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); instruction.Op0Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction); } @@ -1584,11 +1584,11 @@ sealed class OpCodeHandler_Ev_Gv_32_64 : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else { instruction.Op0Kind = OpKind.Memory; @@ -1609,11 +1609,11 @@ sealed class OpCodeHandler_Ev_Gv_Ib : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -1639,11 +1639,11 @@ sealed class OpCodeHandler_Ev_Gv_CL : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -1669,19 +1669,19 @@ sealed class OpCodeHandler_Gv_Mp : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code64); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; } else if (decoder.state.operandSize == OpSize.Size16) { instruction.InternalSetCodeNoCheck(code16); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; } else { instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; } if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); @@ -1704,10 +1704,10 @@ sealed class OpCodeHandler_Gv_Eb : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod == 3) { - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - if ((decoder.state.flags & StateFlags.HasRex) != 0 && index >= 4) + uint index = decoder.state.rm + decoder.state.zs.extraBaseRegisterBase; + if ((decoder.state.zs.flags & StateFlags.HasRex) != 0 && index >= 4) index += 4; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; @@ -1732,11 +1732,11 @@ sealed class OpCodeHandler_Gv_Ew : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op1Kind = OpKind.Memory; @@ -1867,7 +1867,7 @@ sealed class OpCodeHandler_Simple5_ModRM_as : OpCodeHandlerModRM { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); nuint addressSize = (nuint)decoder.state.addressSize; unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[addressSize]); } - instruction.Op0Register = ((int)addressSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)addressSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } } @@ -1882,7 +1882,7 @@ sealed class OpCodeHandler_Simple4 : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) + if ((decoder.state.zs.flags & StateFlags.W) != 0) instruction.InternalSetCodeNoCheck(code64); else instruction.InternalSetCodeNoCheck(code32); @@ -1910,13 +1910,13 @@ sealed class OpCodeHandler_PushSimpleReg : OpCodeHandler { instruction.InternalSetCodeNoCheck(code64); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = index + (int)decoder.state.extraBaseRegisterBase + Register.RAX; + instruction.Op0Register = index + (int)decoder.state.zs.extraBaseRegisterBase + Register.RAX; } else { instruction.InternalSetCodeNoCheck(code16); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = index + (int)decoder.state.extraBaseRegisterBase + Register.AX; + instruction.Op0Register = index + (int)decoder.state.zs.extraBaseRegisterBase + Register.AX; } } else { @@ -1924,13 +1924,13 @@ sealed class OpCodeHandler_PushSimpleReg : OpCodeHandler { instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = index + (int)decoder.state.extraBaseRegisterBase + Register.EAX; + instruction.Op0Register = index + (int)decoder.state.zs.extraBaseRegisterBase + Register.EAX; } else { instruction.InternalSetCodeNoCheck(code16); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = index + (int)decoder.state.extraBaseRegisterBase + Register.AX; + instruction.Op0Register = index + (int)decoder.state.zs.extraBaseRegisterBase + Register.AX; } } } @@ -1958,7 +1958,7 @@ sealed class OpCodeHandler_SimpleReg : OpCodeHandler { //instruction.Op0Kind = OpKind.Register; Static.Assert(Register.AX + 16 == Register.EAX ? 0 : -1); Static.Assert(Register.AX + 32 == Register.RAX ? 0 : -1); - instruction.Op0Register = sizeIndex * 16 + index + (int)decoder.state.extraBaseRegisterBase + Register.AX; + instruction.Op0Register = sizeIndex * 16 + index + (int)decoder.state.zs.extraBaseRegisterBase + Register.AX; } } @@ -2028,7 +2028,7 @@ sealed class OpCodeHandler_Xchg_Reg_rAX : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if (index == 0 && decoder.state.mandatoryPrefix == MandatoryPrefixByte.PF3 && (decoder.options & DecoderOptions.NoPause) == 0) { + if (index == 0 && decoder.state.zs.mandatoryPrefix == MandatoryPrefixByte.PF3 && (decoder.options & DecoderOptions.NoPause) == 0) { decoder.ClearMandatoryPrefixF3(ref instruction); instruction.InternalSetCodeNoCheck(Code.Pause); } @@ -2037,7 +2037,7 @@ sealed class OpCodeHandler_Xchg_Reg_rAX : OpCodeHandler { Static.Assert((int)OpSize.Size32 == 1 ? 0 : -1); Static.Assert((int)OpSize.Size64 == 2 ? 0 : -1); int sizeIndex = (int)decoder.state.operandSize; - int codeIndex = index + (int)decoder.state.extraBaseRegisterBase; + int codeIndex = index + (int)decoder.state.zs.extraBaseRegisterBase; instruction.InternalSetCodeNoCheck(codes[sizeIndex * 16 + codeIndex]); if (codeIndex != 0) { @@ -2127,8 +2127,8 @@ sealed class OpCodeHandler_RegIb3 : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); Register register; - if ((decoder.state.flags & StateFlags.HasRex) != 0) - register = withRexPrefix[index + (int)decoder.state.extraBaseRegisterBase]; + if ((decoder.state.zs.flags & StateFlags.HasRex) != 0) + register = withRexPrefix[index + (int)decoder.state.zs.extraBaseRegisterBase]; else register = index + Register.AL; instruction.InternalSetCodeNoCheck(Code.Mov_r8_imm8); @@ -2154,7 +2154,7 @@ sealed class OpCodeHandler_RegIz2 : OpCodeHandler { instruction.InternalSetCodeNoCheck(Code.Mov_r32_imm32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = index + (int)decoder.state.extraBaseRegisterBase + Register.EAX; + instruction.Op0Register = index + (int)decoder.state.zs.extraBaseRegisterBase + Register.EAX; instruction.Op1Kind = OpKind.Immediate32; instruction.Immediate32 = decoder.ReadUInt32(); } @@ -2162,7 +2162,7 @@ sealed class OpCodeHandler_RegIz2 : OpCodeHandler { instruction.InternalSetCodeNoCheck(Code.Mov_r64_imm64); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = index + (int)decoder.state.extraBaseRegisterBase + Register.RAX; + instruction.Op0Register = index + (int)decoder.state.zs.extraBaseRegisterBase + Register.RAX; instruction.Op1Kind = OpKind.Immediate64; instruction.InternalImmediate64_lo = decoder.ReadUInt32(); instruction.InternalImmediate64_hi = decoder.ReadUInt32(); @@ -2171,7 +2171,7 @@ sealed class OpCodeHandler_RegIz2 : OpCodeHandler { instruction.InternalSetCodeNoCheck(Code.Mov_r16_imm16); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = index + (int)decoder.state.extraBaseRegisterBase + Register.AX; + instruction.Op0Register = index + (int)decoder.state.zs.extraBaseRegisterBase + Register.AX; instruction.Op1Kind = OpKind.Immediate16; instruction.InternalImmediate16 = decoder.ReadUInt16(); } @@ -2273,13 +2273,13 @@ sealed class OpCodeHandler_Gv_Ma : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; } else { instruction.InternalSetCodeNoCheck(code16); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; } Debug.Assert(decoder.state.mod != 3); instruction.Op1Kind = OpKind.Memory; @@ -2301,12 +2301,12 @@ sealed class OpCodeHandler_RvMw_Gw : OpCodeHandlerModRM { Register baseReg; if (decoder.state.operandSize != OpSize.Size16) { instruction.InternalSetCodeNoCheck(code32); - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; baseReg = Register.EAX; } else { instruction.InternalSetCodeNoCheck(code16); - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; baseReg = Register.AX; } Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -2314,7 +2314,7 @@ sealed class OpCodeHandler_RvMw_Gw : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else { instruction.Op0Kind = OpKind.Memory; @@ -2335,11 +2335,11 @@ sealed class OpCodeHandler_Gv_Ev_Ib : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op1Kind = OpKind.Memory; @@ -2371,22 +2371,22 @@ sealed class OpCodeHandler_Gv_Ev_Ib_REX : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; } else { instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; } Debug.Assert(decoder.state.mod == 3); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.XMM0; instruction.Op2Kind = OpKind.Immediate8; instruction.InternalImmediate8 = decoder.ReadByte(); } @@ -2418,11 +2418,11 @@ sealed class OpCodeHandler_Gv_Ev_32_64 : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; if ((disallowReg & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } @@ -2447,11 +2447,11 @@ sealed class OpCodeHandler_Gv_Ev_Iz : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op1Kind = OpKind.Memory; @@ -2786,7 +2786,7 @@ sealed class OpCodeHandler_Ev_Sw : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op0Kind = OpKind.Memory; @@ -2827,7 +2827,7 @@ sealed class OpCodeHandler_Gv_M : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod < 3) { instruction.Op1Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction); @@ -2856,7 +2856,7 @@ sealed class OpCodeHandler_Sw_Ev : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.AX; } else { instruction.Op1Kind = OpKind.Memory; @@ -2927,14 +2927,14 @@ sealed class OpCodeHandler_Reg_Ob : OpCodeHandler { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; instruction.Op0Register = reg; - decoder.displIndex = decoder.state.instructionLength; + decoder.displIndex = decoder.state.zs.instructionLength; //instruction.InternalMemoryIndexScale = 0; //instruction.InternalMemoryBase = Register.None; //instruction.InternalMemoryIndex = Register.None; instruction.Op1Kind = OpKind.Memory; if (decoder.state.addressSize == OpSize.Size64) { instruction.InternalSetMemoryDisplSize(4); - decoder.state.flags |= StateFlags.Addr64; + decoder.state.zs.flags |= StateFlags.Addr64; instruction.MemoryDisplacement64 = decoder.ReadUInt64(); } else if (decoder.state.addressSize == OpSize.Size32) { @@ -2960,7 +2960,7 @@ sealed class OpCodeHandler_Ob_Reg : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); instruction.InternalSetCodeNoCheck(code); - decoder.displIndex = decoder.state.instructionLength; + decoder.displIndex = decoder.state.zs.instructionLength; //instruction.InternalMemoryIndexScale = 0; //instruction.InternalMemoryBase = Register.None; //instruction.InternalMemoryIndex = Register.None; @@ -2970,7 +2970,7 @@ sealed class OpCodeHandler_Ob_Reg : OpCodeHandler { instruction.Op1Register = reg; if (decoder.state.addressSize == OpSize.Size64) { instruction.InternalSetMemoryDisplSize(4); - decoder.state.flags |= StateFlags.Addr64; + decoder.state.zs.flags |= StateFlags.Addr64; instruction.MemoryDisplacement64 = decoder.ReadUInt64(); } else if (decoder.state.addressSize == OpSize.Size32) { @@ -2992,7 +2992,7 @@ sealed class OpCodeHandler_Reg_Ov : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - decoder.displIndex = decoder.state.instructionLength; + decoder.displIndex = decoder.state.zs.instructionLength; //instruction.InternalMemoryIndexScale = 0; //instruction.InternalMemoryBase = Register.None; //instruction.InternalMemoryIndex = Register.None; @@ -3004,7 +3004,7 @@ sealed class OpCodeHandler_Reg_Ov : OpCodeHandler { instruction.Op0Register = ((int)operandSize << 4) + Register.AX; if (decoder.state.addressSize == OpSize.Size64) { instruction.InternalSetMemoryDisplSize(4); - decoder.state.flags |= StateFlags.Addr64; + decoder.state.zs.flags |= StateFlags.Addr64; instruction.MemoryDisplacement64 = decoder.ReadUInt64(); } else if (decoder.state.addressSize == OpSize.Size32) { @@ -3026,7 +3026,7 @@ sealed class OpCodeHandler_Ov_Reg : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - decoder.displIndex = decoder.state.instructionLength; + decoder.displIndex = decoder.state.zs.instructionLength; //instruction.InternalMemoryIndexScale = 0; //instruction.InternalMemoryBase = Register.None; //instruction.InternalMemoryIndex = Register.None; @@ -3038,7 +3038,7 @@ sealed class OpCodeHandler_Ov_Reg : OpCodeHandler { instruction.Op1Register = ((int)operandSize << 4) + Register.AX; if (decoder.state.addressSize == OpSize.Size64) { instruction.InternalSetMemoryDisplSize(4); - decoder.state.flags |= StateFlags.Addr64; + decoder.state.zs.flags |= StateFlags.Addr64; instruction.MemoryDisplacement64 = decoder.ReadUInt64(); } else if (decoder.state.addressSize == OpSize.Size32) { @@ -3269,13 +3269,13 @@ sealed class OpCodeHandler_Eb_Ib : OpCodeHandlerModRM { if (decoder.state.mod < 3) { Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); Static.Assert((int)StateFlags.AllowLock == 0x00002000 ? 0 : -1); - decoder.state.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); + decoder.state.zs.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); instruction.Op0Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction); } else { - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - if ((decoder.state.flags & StateFlags.HasRex) != 0 && index >= 4) + uint index = decoder.state.rm + decoder.state.zs.extraBaseRegisterBase; + if ((decoder.state.zs.flags & StateFlags.HasRex) != 0 && index >= 4) index += 4; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; @@ -3296,10 +3296,10 @@ sealed class OpCodeHandler_Eb_1 : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); instruction.Op1Kind = OpKind.Immediate8; instruction.InternalImmediate8 = 1; - decoder.state.flags |= StateFlags.NoImm; + decoder.state.zs.flags |= StateFlags.NoImm; if (decoder.state.mod == 3) { - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - if ((decoder.state.flags & StateFlags.HasRex) != 0 && index >= 4) + uint index = decoder.state.rm + decoder.state.zs.extraBaseRegisterBase; + if ((decoder.state.zs.flags & StateFlags.HasRex) != 0 && index >= 4) index += 4; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; @@ -3324,8 +3324,8 @@ sealed class OpCodeHandler_Eb_CL : OpCodeHandlerModRM { //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = Register.CL; if (decoder.state.mod == 3) { - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - if ((decoder.state.flags & StateFlags.HasRex) != 0 && index >= 4) + uint index = decoder.state.rm + decoder.state.zs.extraBaseRegisterBase; + if ((decoder.state.zs.flags & StateFlags.HasRex) != 0 && index >= 4) index += 4; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; @@ -3353,8 +3353,8 @@ sealed class OpCodeHandler_Eb : OpCodeHandlerModRM { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); instruction.InternalSetCodeNoCheck(code); if (decoder.state.mod == 3) { - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - if ((decoder.state.flags & StateFlags.HasRex) != 0 && index >= 4) + uint index = decoder.state.rm + decoder.state.zs.extraBaseRegisterBase; + if ((decoder.state.zs.flags & StateFlags.HasRex) != 0 && index >= 4) index += 4; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; @@ -3363,7 +3363,7 @@ sealed class OpCodeHandler_Eb : OpCodeHandlerModRM { else { Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); Static.Assert((int)StateFlags.AllowLock == 0x00002000 ? 0 : -1); - decoder.state.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); + decoder.state.zs.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); instruction.Op0Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction); } @@ -3385,15 +3385,15 @@ sealed class OpCodeHandler_Eb_Gb : OpCodeHandlerModRM { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); instruction.InternalSetCodeNoCheck(code); uint index; - index = decoder.state.reg + decoder.state.extraRegisterBase; - if ((decoder.state.flags & StateFlags.HasRex) != 0 && index >= 4) + index = decoder.state.reg + decoder.state.zs.extraRegisterBase; + if ((decoder.state.zs.flags & StateFlags.HasRex) != 0 && index >= 4) index += 4; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)index + Register.AL; if (decoder.state.mod == 3) { - index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - if ((decoder.state.flags & StateFlags.HasRex) != 0 && index >= 4) + index = decoder.state.rm + decoder.state.zs.extraBaseRegisterBase; + if ((decoder.state.zs.flags & StateFlags.HasRex) != 0 && index >= 4) index += 4; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; @@ -3402,7 +3402,7 @@ sealed class OpCodeHandler_Eb_Gb : OpCodeHandlerModRM { else { Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); Static.Assert((int)StateFlags.AllowLock == 0x00002000 ? 0 : -1); - decoder.state.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); + decoder.state.zs.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); instruction.Op0Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction); } @@ -3417,16 +3417,16 @@ sealed class OpCodeHandler_Gb_Eb : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); instruction.InternalSetCodeNoCheck(code); - uint index = decoder.state.reg + decoder.state.extraRegisterBase; - if ((decoder.state.flags & StateFlags.HasRex) != 0 && index >= 4) + uint index = decoder.state.reg + decoder.state.zs.extraRegisterBase; + if ((decoder.state.zs.flags & StateFlags.HasRex) != 0 && index >= 4) index += 4; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; instruction.Op0Register = (int)index + Register.AL; if (decoder.state.mod == 3) { - index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - if ((decoder.state.flags & StateFlags.HasRex) != 0 && index >= 4) + index = decoder.state.rm + decoder.state.zs.extraBaseRegisterBase; + if ((decoder.state.zs.flags & StateFlags.HasRex) != 0 && index >= 4) index += 4; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; @@ -3455,7 +3455,7 @@ sealed class OpCodeHandler_M : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) + if ((decoder.state.zs.flags & StateFlags.W) != 0) instruction.InternalSetCodeNoCheck(codeW1); else instruction.InternalSetCodeNoCheck(codeW0); @@ -3488,7 +3488,7 @@ sealed class OpCodeHandler_M_REXW : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) + if ((decoder.state.zs.flags & StateFlags.W) != 0) instruction.InternalSetCodeNoCheck(code64); else instruction.InternalSetCodeNoCheck(code32); @@ -3496,12 +3496,12 @@ sealed class OpCodeHandler_M_REXW : OpCodeHandlerModRM { decoder.SetInvalidInstruction(); else { instruction.Op0Kind = OpKind.Memory; - var flags = (decoder.state.flags & StateFlags.W) != 0 ? flags64 : flags32; + var flags = (decoder.state.zs.flags & StateFlags.W) != 0 ? flags64 : flags32; if ((flags & (HandlerFlags.Xacquire | HandlerFlags.Xrelease)) != 0) decoder.SetXacquireXrelease(ref instruction); Static.Assert((int)HandlerFlags.Lock == 8 ? 0 : -1); Static.Assert((int)StateFlags.AllowLock == 0x00002000 ? 0 : -1); - decoder.state.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); + decoder.state.zs.flags |= (StateFlags)((uint)(flags & HandlerFlags.Lock) << (13 - 3)); decoder.ReadOpMem(ref instruction); } } @@ -3547,12 +3547,12 @@ sealed class OpCodeHandler_VW : OpCodeHandlerModRM { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod == 3) { instruction.InternalSetCodeNoCheck(codeR); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.XMM0; } else { instruction.InternalSetCodeNoCheck(codeM); @@ -3572,7 +3572,7 @@ sealed class OpCodeHandler_WV : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod < 3) { instruction.Op0Kind = OpKind.Memory; decoder.ReadOpMem(ref instruction); @@ -3580,7 +3580,7 @@ sealed class OpCodeHandler_WV : OpCodeHandlerModRM { else { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.XMM0; } } } @@ -3601,11 +3601,11 @@ sealed class OpCodeHandler_rDI_VX_RX : OpCodeHandlerModRM { instruction.Op0Kind = OpKind.MemorySegDI; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.XMM0; + instruction.Op2Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.XMM0; } else decoder.SetInvalidInstruction(); @@ -3649,7 +3649,7 @@ sealed class OpCodeHandler_VM : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { @@ -3669,7 +3669,7 @@ sealed class OpCodeHandler_MV : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { @@ -3689,7 +3689,7 @@ sealed class OpCodeHandler_VQ : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; @@ -3807,7 +3807,7 @@ sealed class OpCodeHandler_P_W : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.XMM0; } else { instruction.Op1Kind = OpKind.Memory; @@ -3830,7 +3830,7 @@ sealed class OpCodeHandler_P_R : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.XMM0; } else decoder.SetInvalidInstruction(); @@ -3849,7 +3849,7 @@ sealed class OpCodeHandler_P_Ev : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); Register gpr; - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -3863,7 +3863,7 @@ sealed class OpCodeHandler_P_Ev : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op1Kind = OpKind.Memory; @@ -3884,7 +3884,7 @@ sealed class OpCodeHandler_P_Ev_Ib : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); Register gpr; - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -3898,7 +3898,7 @@ sealed class OpCodeHandler_P_Ev_Ib : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op1Kind = OpKind.Memory; @@ -3924,7 +3924,7 @@ sealed class OpCodeHandler_Ev_P : OpCodeHandlerModRM { //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.reg + Register.MM0; Register gpr; - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -3935,7 +3935,7 @@ sealed class OpCodeHandler_Ev_P : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op0Kind = OpKind.Memory; @@ -3955,22 +3955,22 @@ sealed class OpCodeHandler_Gv_W : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(codeW1); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; } else { instruction.InternalSetCodeNoCheck(codeW0); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; } if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.XMM0; } else { instruction.Op1Kind = OpKind.Memory; @@ -4001,11 +4001,11 @@ sealed class OpCodeHandler_V_Ev : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op1Kind = OpKind.Memory; @@ -4030,17 +4030,17 @@ sealed class OpCodeHandler_VWIb : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) + if ((decoder.state.zs.flags & StateFlags.W) != 0) instruction.InternalSetCodeNoCheck(codeW1); else instruction.InternalSetCodeNoCheck(codeW0); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.XMM0; } else { instruction.Op1Kind = OpKind.Memory; @@ -4061,11 +4061,11 @@ sealed class OpCodeHandler_VRIbIb : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.XMM0; } else decoder.SetInvalidInstruction(); @@ -4087,7 +4087,7 @@ sealed class OpCodeHandler_RIbIb : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.XMM0; } else decoder.SetInvalidInstruction(); @@ -4109,7 +4109,7 @@ sealed class OpCodeHandler_RIb : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.XMM0; } else decoder.SetInvalidInstruction(); @@ -4131,9 +4131,9 @@ sealed class OpCodeHandler_Ed_V_Ib : OpCodeHandlerModRM { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; Register gpr; - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -4144,7 +4144,7 @@ sealed class OpCodeHandler_Ed_V_Ib : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op0Kind = OpKind.Memory; @@ -4167,7 +4167,7 @@ sealed class OpCodeHandler_VX_Ev : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); Register gpr; - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -4177,11 +4177,11 @@ sealed class OpCodeHandler_VX_Ev : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op1Kind = OpKind.Memory; @@ -4203,9 +4203,9 @@ sealed class OpCodeHandler_Ev_VX : OpCodeHandlerModRM { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; Register gpr; - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -4216,7 +4216,7 @@ sealed class OpCodeHandler_Ev_VX : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op0Kind = OpKind.Memory; @@ -4237,7 +4237,7 @@ sealed class OpCodeHandler_VX_E_Ib : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); Register gpr; - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -4247,11 +4247,11 @@ sealed class OpCodeHandler_VX_E_Ib : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op1Kind = OpKind.Memory; @@ -4273,20 +4273,20 @@ sealed class OpCodeHandler_Gv_RX : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) + if ((decoder.state.zs.flags & StateFlags.W) != 0) instruction.InternalSetCodeNoCheck(code64); else instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - if ((decoder.state.flags & StateFlags.W) != 0) - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + if ((decoder.state.zs.flags & StateFlags.W) != 0) + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; else - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.XMM0; } else decoder.SetInvalidInstruction(); @@ -4300,7 +4300,7 @@ sealed class OpCodeHandler_B_MIB : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if (decoder.state.reg > 3 || (decoder.state.extraRegisterBase & decoder.invalidCheckMask) != 0) + if (decoder.state.reg > 3 || (decoder.state.zs.extraRegisterBase & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -4322,7 +4322,7 @@ sealed class OpCodeHandler_MIB_B : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if (decoder.state.reg > 3 || (decoder.state.extraRegisterBase & decoder.invalidCheckMask) != 0) + if (decoder.state.reg > 3 || (decoder.state.zs.extraRegisterBase & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -4348,7 +4348,7 @@ sealed class OpCodeHandler_B_BM : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if (decoder.state.reg > 3 || (decoder.state.extraRegisterBase & decoder.invalidCheckMask) != 0) + if (decoder.state.reg > 3 || (decoder.state.zs.extraRegisterBase & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); if (decoder.is64bMode) instruction.InternalSetCodeNoCheck(code64); @@ -4361,7 +4361,7 @@ sealed class OpCodeHandler_B_BM : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.rm + Register.BND0; - if (decoder.state.rm > 3 || (decoder.state.extraBaseRegisterBase & decoder.invalidCheckMask) != 0) + if (decoder.state.rm > 3 || (decoder.state.zs.extraBaseRegisterBase & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { @@ -4382,7 +4382,7 @@ sealed class OpCodeHandler_BM_B : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if (decoder.state.reg > 3 || ((decoder.state.extraRegisterBase & decoder.invalidCheckMask) != 0)) + if (decoder.state.reg > 3 || ((decoder.state.zs.extraRegisterBase & decoder.invalidCheckMask) != 0)) decoder.SetInvalidInstruction(); if (decoder.is64bMode) instruction.InternalSetCodeNoCheck(code64); @@ -4395,7 +4395,7 @@ sealed class OpCodeHandler_BM_B : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; instruction.Op0Register = (int)decoder.state.rm + Register.BND0; - if (decoder.state.rm > 3 || (decoder.state.extraBaseRegisterBase & decoder.invalidCheckMask) != 0) + if (decoder.state.rm > 3 || (decoder.state.zs.extraBaseRegisterBase & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); } else { @@ -4418,7 +4418,7 @@ sealed class OpCodeHandler_B_Ev : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if (decoder.state.reg > 3 || (decoder.state.extraRegisterBase & decoder.invalidCheckMask) != 0) + if (decoder.state.reg > 3 || (decoder.state.zs.extraRegisterBase & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register baseReg; if (decoder.is64bMode) { @@ -4435,7 +4435,7 @@ sealed class OpCodeHandler_B_Ev : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else { instruction.Op1Kind = OpKind.Memory; @@ -4458,17 +4458,17 @@ sealed class OpCodeHandler_Mv_Gv_REXW : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; } else { instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; } if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); @@ -4490,16 +4490,16 @@ sealed class OpCodeHandler_Gv_N_Ib_REX : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) + if ((decoder.state.zs.flags & StateFlags.W) != 0) instruction.InternalSetCodeNoCheck(code64); else instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - if ((decoder.state.flags & StateFlags.W) != 0) - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + if ((decoder.state.zs.flags & StateFlags.W) != 0) + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; else - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; @@ -4523,16 +4523,16 @@ sealed class OpCodeHandler_Gv_N : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) + if ((decoder.state.zs.flags & StateFlags.W) != 0) instruction.InternalSetCodeNoCheck(code64); else instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - if ((decoder.state.flags & StateFlags.W) != 0) - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + if ((decoder.state.zs.flags & StateFlags.W) != 0) + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; else - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; @@ -4553,7 +4553,7 @@ sealed class OpCodeHandler_VN : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; @@ -4576,7 +4576,7 @@ sealed class OpCodeHandler_Gv_Mv : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op0Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { @@ -4598,7 +4598,7 @@ sealed class OpCodeHandler_Mv_Gv : OpCodeHandlerModRM { unsafe { instruction.InternalSetCodeNoCheck((Code)codes.codes[operandSize]); } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.AX; + instruction.Op1Register = ((int)operandSize << 4) + (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.AX; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { @@ -4619,21 +4619,21 @@ sealed class OpCodeHandler_Gv_Eb_REX : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; } else { instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; } if (decoder.state.mod == 3) { - uint index = decoder.state.rm + decoder.state.extraBaseRegisterBase; - if ((decoder.state.flags & StateFlags.HasRex) != 0 && index >= 4) + uint index = decoder.state.rm + decoder.state.zs.extraBaseRegisterBase; + if ((decoder.state.zs.flags & StateFlags.HasRex) != 0 && index >= 4) index += 4; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; @@ -4657,25 +4657,25 @@ sealed class OpCodeHandler_Gv_Ev_REX : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; } else { instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; } if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - if ((decoder.state.flags & StateFlags.W) != 0) - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.RAX; + if ((decoder.state.zs.flags & StateFlags.W) != 0) + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.RAX; else - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.EAX; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.EAX; } else { instruction.Op1Kind = OpKind.Memory; @@ -4695,17 +4695,17 @@ sealed class OpCodeHandler_Ev_Gv_REX : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; } else { instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; } Debug.Assert(decoder.state.mod != 3); instruction.Op0Kind = OpKind.Memory; @@ -4726,9 +4726,9 @@ sealed class OpCodeHandler_GvM_VX_Ib : OpCodeHandlerModRM { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; Register gpr; - if ((decoder.state.flags & StateFlags.W) != 0) { + if ((decoder.state.zs.flags & StateFlags.W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -4739,7 +4739,7 @@ sealed class OpCodeHandler_GvM_VX_Ib : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op0Kind = OpKind.Memory; @@ -4755,7 +4755,7 @@ sealed class OpCodeHandler_Wbinvd : OpCodeHandler { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.Legacy); - if ((decoder.options & DecoderOptions.NoWbnoinvd) != 0 || decoder.state.mandatoryPrefix != MandatoryPrefixByte.PF3) + if ((decoder.options & DecoderOptions.NoWbnoinvd) != 0 || decoder.state.zs.mandatoryPrefix != MandatoryPrefixByte.PF3) instruction.InternalSetCodeNoCheck(Code.Wbinvd); else { decoder.ClearMandatoryPrefixF3(ref instruction); diff --git a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_MVEX.cs b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_MVEX.cs index 51cc86202..e4f3bee26 100644 --- a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_MVEX.cs +++ b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_MVEX.cs @@ -19,7 +19,7 @@ sealed class OpCodeHandler_EH : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.MVEX); - ((decoder.state.flags & StateFlags.MvexEH) != 0 ? handlerEH1 : handlerEH0).Decode(decoder, ref instruction); + ((decoder.state.zs.flags & StateFlags.MvexEH) != 0 ? handlerEH1 : handlerEH0).Decode(decoder, ref instruction); } } @@ -68,14 +68,14 @@ sealed class OpCodeHandler_MVEX_MV : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; var mvex = new MvexInfo(code); var sss = decoder.state.Sss; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { instruction.Op0Kind = OpKind.Memory; - if (mvex.CanUseEvictionHint && (decoder.state.flags & StateFlags.MvexEH) != 0) + if (mvex.CanUseEvictionHint && (decoder.state.zs.flags & StateFlags.MvexEH) != 0) instruction.InternalSetIsMvexEvictionHint(); if ((mvex.InvalidConvFns & (1U << sss) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); @@ -103,14 +103,14 @@ sealed class OpCodeHandler_MVEX_VW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; var mvex = new MvexInfo(code); var sss = decoder.state.Sss; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + Register.ZMM0; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) { + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) { if (mvex.CanUseSuppressAllExceptions) { if ((sss & 4) != 0) instruction.InternalSetSuppressAllExceptions(); @@ -135,7 +135,7 @@ sealed class OpCodeHandler_MVEX_VW : OpCodeHandlerModRM { } else { instruction.Op1Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) instruction.InternalSetIsMvexEvictionHint(); if ((mvex.InvalidConvFns & (1U << sss) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); @@ -168,7 +168,7 @@ sealed class OpCodeHandler_MVEX_HWIb : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + Register.ZMM0; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) { + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) { if (mvex.CanUseSuppressAllExceptions) { if ((sss & 4) != 0) instruction.InternalSetSuppressAllExceptions(); @@ -193,7 +193,7 @@ sealed class OpCodeHandler_MVEX_HWIb : OpCodeHandlerModRM { } else { instruction.Op1Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) instruction.InternalSetIsMvexEvictionHint(); if ((mvex.InvalidConvFns & (1U << sss) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); @@ -223,14 +223,14 @@ sealed class OpCodeHandler_MVEX_VWIb : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; var mvex = new MvexInfo(code); var sss = decoder.state.Sss; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + Register.ZMM0; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) { + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) { if (mvex.CanUseSuppressAllExceptions) { if ((sss & 4) != 0) instruction.InternalSetSuppressAllExceptions(); @@ -255,7 +255,7 @@ sealed class OpCodeHandler_MVEX_VWIb : OpCodeHandlerModRM { } else { instruction.Op1Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) instruction.InternalSetIsMvexEvictionHint(); if ((mvex.InvalidConvFns & (1U << sss) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); @@ -283,7 +283,7 @@ sealed class OpCodeHandler_MVEX_VHW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + Register.ZMM0; @@ -295,7 +295,7 @@ sealed class OpCodeHandler_MVEX_VHW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + Register.ZMM0; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) { + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) { if (mvex.CanUseSuppressAllExceptions) { if ((sss & 4) != 0) instruction.InternalSetSuppressAllExceptions(); @@ -320,7 +320,7 @@ sealed class OpCodeHandler_MVEX_VHW : OpCodeHandlerModRM { } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) instruction.InternalSetIsMvexEvictionHint(); if ((mvex.InvalidConvFns & (1U << sss) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); @@ -346,7 +346,7 @@ sealed class OpCodeHandler_MVEX_VHWIb : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + Register.ZMM0; @@ -356,7 +356,7 @@ sealed class OpCodeHandler_MVEX_VHWIb : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + Register.ZMM0; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) { + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) { if (mvex.CanUseSuppressAllExceptions) { if ((sss & 4) != 0) instruction.InternalSetSuppressAllExceptions(); @@ -381,7 +381,7 @@ sealed class OpCodeHandler_MVEX_VHWIb : OpCodeHandlerModRM { } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) instruction.InternalSetIsMvexEvictionHint(); if ((mvex.InvalidConvFns & (1U << sss) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); @@ -411,7 +411,7 @@ sealed class OpCodeHandler_MVEX_VKW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = ((int)decoder.state.vvvv & 7) + Register.K0; @@ -421,7 +421,7 @@ sealed class OpCodeHandler_MVEX_VKW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + Register.ZMM0; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) { + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) { if (mvex.CanUseSuppressAllExceptions) { if ((sss & 4) != 0) instruction.InternalSetSuppressAllExceptions(); @@ -446,7 +446,7 @@ sealed class OpCodeHandler_MVEX_VKW : OpCodeHandlerModRM { } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) instruction.InternalSetIsMvexEvictionHint(); if ((mvex.InvalidConvFns & (1U << sss) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); @@ -476,7 +476,7 @@ sealed class OpCodeHandler_MVEX_KHW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + Register.ZMM0; - if (((decoder.state.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) + if (((decoder.state.zs.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); var mvex = new MvexInfo(code); var sss = decoder.state.Sss; @@ -484,7 +484,7 @@ sealed class OpCodeHandler_MVEX_KHW : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + Register.ZMM0; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) { + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) { if (mvex.CanUseSuppressAllExceptions) { if ((sss & 4) != 0) instruction.InternalSetSuppressAllExceptions(); @@ -509,7 +509,7 @@ sealed class OpCodeHandler_MVEX_KHW : OpCodeHandlerModRM { } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) instruction.InternalSetIsMvexEvictionHint(); if ((mvex.InvalidConvFns & (1U << sss) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); @@ -545,7 +545,7 @@ sealed class OpCodeHandler_MVEX_KHWIb : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBaseEVEX) + Register.ZMM0; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) { + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) { if (mvex.CanUseSuppressAllExceptions) { if ((sss & 4) != 0) instruction.InternalSetSuppressAllExceptions(); @@ -570,14 +570,14 @@ sealed class OpCodeHandler_MVEX_KHWIb : OpCodeHandlerModRM { } else { instruction.Op2Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) instruction.InternalSetIsMvexEvictionHint(); if ((mvex.InvalidConvFns & (1U << sss) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetMvexRegMemConv(MvexRegMemConv.MemConvNone + sss); decoder.ReadOpMem(ref instruction, mvex.GetTupleType(sss)); } - if (((decoder.state.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) + if (((decoder.state.zs.extraRegisterBase | decoder.state.extraRegisterBaseEVEX) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.Op3Kind = OpKind.Immediate8; instruction.Immediate8 = (byte)decoder.ReadByte(); @@ -606,7 +606,7 @@ sealed class OpCodeHandler_MVEX_VSIB : OpCodeHandlerModRM { decoder.SetInvalidInstruction(); else { instruction.Op0Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) instruction.InternalSetIsMvexEvictionHint(); if ((mvex.InvalidConvFns & (1U << sss) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); @@ -634,14 +634,14 @@ sealed class OpCodeHandler_MVEX_VSIB_V : OpCodeHandlerModRM { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX) + Register.ZMM0; var mvex = new MvexInfo(code); var sss = decoder.state.Sss; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { instruction.Op0Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) instruction.InternalSetIsMvexEvictionHint(); if ((mvex.InvalidConvFns & (1U << sss) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); @@ -667,7 +667,7 @@ sealed class OpCodeHandler_MVEX_V_VSIB : OpCodeHandlerModRM { decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); - int regNum = (int)(decoder.state.reg + decoder.state.extraRegisterBase + decoder.state.extraRegisterBaseEVEX); + int regNum = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase + decoder.state.extraRegisterBaseEVEX); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; instruction.Op0Register = regNum + Register.ZMM0; @@ -677,7 +677,7 @@ sealed class OpCodeHandler_MVEX_V_VSIB : OpCodeHandlerModRM { decoder.SetInvalidInstruction(); else { instruction.Op1Kind = OpKind.Memory; - if ((decoder.state.flags & StateFlags.MvexEH) != 0) + if ((decoder.state.zs.flags & StateFlags.MvexEH) != 0) instruction.InternalSetIsMvexEvictionHint(); if ((mvex.InvalidConvFns & (1U << sss) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); diff --git a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_VEX.cs b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_VEX.cs index cb5e1aabf..1127d3def 100644 --- a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_VEX.cs +++ b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_VEX.cs @@ -79,7 +79,7 @@ sealed class OpCodeHandler_VEX_VHEv : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(codeW1); gpr = Register.RAX; } @@ -89,14 +89,14 @@ sealed class OpCodeHandler_VEX_VHEv : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op2Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op2Kind = OpKind.Memory; @@ -119,7 +119,7 @@ sealed class OpCodeHandler_VEX_VHEvIb : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(codeW1); gpr = Register.RAX; } @@ -129,14 +129,14 @@ sealed class OpCodeHandler_VEX_VHEvIb : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op2Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op2Kind = OpKind.Memory; @@ -171,11 +171,11 @@ sealed class OpCodeHandler_VEX_VW : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg1; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg2; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg2; } else { instruction.Op1Kind = OpKind.Memory; @@ -198,7 +198,7 @@ sealed class OpCodeHandler_VEX_VX_Ev : OpCodeHandlerModRM { if ((decoder.state.vvvv_invalidCheck & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -208,11 +208,11 @@ sealed class OpCodeHandler_VEX_VX_Ev : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op1Kind = OpKind.Memory; @@ -236,9 +236,9 @@ sealed class OpCodeHandler_VEX_Ev_VX : OpCodeHandlerModRM { decoder.SetInvalidInstruction(); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.XMM0; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.XMM0; Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -249,7 +249,7 @@ sealed class OpCodeHandler_VEX_Ev_VX : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op0Kind = OpKind.Memory; @@ -276,11 +276,11 @@ sealed class OpCodeHandler_VEX_WV : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg1; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg1; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg2; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg2; } else { instruction.Op0Kind = OpKind.Memory; @@ -305,7 +305,7 @@ sealed class OpCodeHandler_VEX_VM : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { @@ -331,7 +331,7 @@ sealed class OpCodeHandler_VEX_MV : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { @@ -373,17 +373,17 @@ sealed class OpCodeHandler_VEX_RdRq : OpCodeHandlerModRM { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); if ((decoder.state.vvvv_invalidCheck & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.RAX; } else { instruction.InternalSetCodeNoCheck(code32); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.EAX; } if (decoder.state.mod != 3) decoder.SetInvalidInstruction(); @@ -412,11 +412,11 @@ sealed class OpCodeHandler_VEX_rDI_VX_RX : OpCodeHandlerModRM { instruction.Op0Kind = OpKind.MemorySegDI; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op2Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else decoder.SetInvalidInstruction(); @@ -447,17 +447,17 @@ sealed class OpCodeHandler_VEX_VWIb : OpCodeHandlerModRM { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); if ((decoder.state.vvvv_invalidCheck & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) instruction.InternalSetCodeNoCheck(codeW1); else instruction.InternalSetCodeNoCheck(codeW0); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg1; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg2; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg2; } else { instruction.Op1Kind = OpKind.Memory; @@ -487,7 +487,7 @@ sealed class OpCodeHandler_VEX_WVIb : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg1; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg1; } else { instruction.Op0Kind = OpKind.Memory; @@ -495,7 +495,7 @@ sealed class OpCodeHandler_VEX_WVIb : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg2; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg2; instruction.Op2Kind = OpKind.Immediate8; instruction.InternalImmediate8 = decoder.ReadByte(); } @@ -517,7 +517,7 @@ sealed class OpCodeHandler_VEX_Ed_V_Ib : OpCodeHandlerModRM { if ((decoder.state.vvvv_invalidCheck & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -528,7 +528,7 @@ sealed class OpCodeHandler_VEX_Ed_V_Ib : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op0Kind = OpKind.Memory; @@ -536,7 +536,7 @@ sealed class OpCodeHandler_VEX_Ed_V_Ib : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; instruction.Op2Kind = OpKind.Immediate8; instruction.InternalImmediate8 = decoder.ReadByte(); } @@ -577,7 +577,7 @@ sealed class OpCodeHandler_VEX_VHW : OpCodeHandlerModRM { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg1; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg2; @@ -585,7 +585,7 @@ sealed class OpCodeHandler_VEX_VHW : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(codeR); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg3; + instruction.Op2Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg3; } else { instruction.InternalSetCodeNoCheck(codeM); @@ -609,14 +609,14 @@ sealed class OpCodeHandler_VEX_VWH : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)decoder.state.vvvv + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else { instruction.Op1Kind = OpKind.Memory; @@ -640,13 +640,13 @@ sealed class OpCodeHandler_VEX_WHV : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(codeR); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op2Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; } } @@ -664,7 +664,7 @@ sealed class OpCodeHandler_VEX_VHM : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; @@ -694,7 +694,7 @@ sealed class OpCodeHandler_VEX_MHV : OpCodeHandlerModRM { instruction.Op1Register = (int)decoder.state.vvvv + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op2Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; if (decoder.state.mod == 3) decoder.SetInvalidInstruction(); else { @@ -729,14 +729,14 @@ sealed class OpCodeHandler_VEX_VHWIb : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg1; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg1; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg2; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg3; + instruction.Op2Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg3; } else { instruction.Op2Kind = OpKind.Memory; @@ -765,7 +765,7 @@ sealed class OpCodeHandler_VEX_HRIb : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else decoder.SetInvalidInstruction(); @@ -788,14 +788,14 @@ sealed class OpCodeHandler_VEX_VHWIs4 : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op2Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else { instruction.Op2Kind = OpKind.Memory; @@ -821,14 +821,14 @@ sealed class OpCodeHandler_VEX_VHIs4W : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op3Kind = OpKind.Register; - instruction.Op3Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op3Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else { instruction.Op3Kind = OpKind.Memory; @@ -854,14 +854,14 @@ sealed class OpCodeHandler_VEX_VHWIs5 : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op2Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else { instruction.Op2Kind = OpKind.Memory; @@ -890,14 +890,14 @@ sealed class OpCodeHandler_VEX_VHIs5W : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + baseReg; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op3Kind = OpKind.Register; - instruction.Op3Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op3Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else { instruction.Op3Kind = OpKind.Memory; @@ -919,7 +919,7 @@ sealed class OpCodeHandler_VEX_VK_HK_RK : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - if (decoder.invalidCheckMask != 0 && (decoder.state.vvvv > 7 || decoder.state.extraRegisterBase != 0)) + if (decoder.invalidCheckMask != 0 && (decoder.state.vvvv > 7 || decoder.state.zs.extraRegisterBase != 0)) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -945,7 +945,7 @@ sealed class OpCodeHandler_VEX_VK_RK : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - if (((decoder.state.vvvv_invalidCheck | decoder.state.extraRegisterBase) & decoder.invalidCheckMask) != 0) + if (((decoder.state.vvvv_invalidCheck | decoder.state.zs.extraRegisterBase) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -968,7 +968,7 @@ sealed class OpCodeHandler_VEX_VK_RK_Ib : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - if (((decoder.state.vvvv_invalidCheck | decoder.state.extraRegisterBase) & decoder.invalidCheckMask) != 0) + if (((decoder.state.vvvv_invalidCheck | decoder.state.zs.extraRegisterBase) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -993,7 +993,7 @@ sealed class OpCodeHandler_VEX_VK_WK : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - if (((decoder.state.vvvv_invalidCheck | decoder.state.extraRegisterBase) & decoder.invalidCheckMask) != 0) + if (((decoder.state.vvvv_invalidCheck | decoder.state.zs.extraRegisterBase) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -1018,7 +1018,7 @@ sealed class OpCodeHandler_VEX_M_VK : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - if (((decoder.state.vvvv_invalidCheck | decoder.state.extraRegisterBase) & decoder.invalidCheckMask) != 0) + if (((decoder.state.vvvv_invalidCheck | decoder.state.zs.extraRegisterBase) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -1044,7 +1044,7 @@ sealed class OpCodeHandler_VEX_VK_R : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - if (((decoder.state.vvvv_invalidCheck | decoder.state.extraRegisterBase) & decoder.invalidCheckMask) != 0) + if (((decoder.state.vvvv_invalidCheck | decoder.state.zs.extraRegisterBase) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -1053,7 +1053,7 @@ sealed class OpCodeHandler_VEX_VK_R : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else decoder.SetInvalidInstruction(); @@ -1076,7 +1076,7 @@ sealed class OpCodeHandler_VEX_G_VK : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + gpr; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; @@ -1102,22 +1102,22 @@ sealed class OpCodeHandler_VEX_Gv_W : OpCodeHandlerModRM { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); if ((decoder.state.vvvv_invalidCheck & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(codeW1); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; } else { instruction.InternalSetCodeNoCheck(codeW0); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.EAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.EAX; } if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else { instruction.Op1Kind = OpKind.Memory; @@ -1142,7 +1142,7 @@ sealed class OpCodeHandler_VEX_Gv_RX : OpCodeHandlerModRM { if ((decoder.state.vvvv_invalidCheck & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -1152,11 +1152,11 @@ sealed class OpCodeHandler_VEX_Gv_RX : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + gpr; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else decoder.SetInvalidInstruction(); @@ -1179,7 +1179,7 @@ sealed class OpCodeHandler_VEX_Gv_GPR_Ib : OpCodeHandlerModRM { if ((decoder.state.vvvv_invalidCheck & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -1189,11 +1189,11 @@ sealed class OpCodeHandler_VEX_Gv_GPR_Ib : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + gpr; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + baseReg; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + baseReg; } else decoder.SetInvalidInstruction(); @@ -1218,7 +1218,7 @@ sealed class OpCodeHandler_VEX_VX_VSIB_HX : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); instruction.InternalSetCodeNoCheck(code); - int regNum = (int)(decoder.state.reg + decoder.state.extraRegisterBase); + int regNum = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; instruction.Op0Register = regNum + baseReg1; @@ -1251,7 +1251,7 @@ sealed class OpCodeHandler_VEX_Gv_Gv_Ev : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -1261,14 +1261,14 @@ sealed class OpCodeHandler_VEX_Gv_Gv_Ev : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + gpr; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.vvvv + gpr; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; - instruction.Op2Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op2Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op2Kind = OpKind.Memory; @@ -1289,7 +1289,7 @@ sealed class OpCodeHandler_VEX_Gv_Ev_Gv : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -1299,14 +1299,14 @@ sealed class OpCodeHandler_VEX_Gv_Ev_Gv : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + gpr; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op2Kind = OpKind.Register; instruction.Op2Register = (int)decoder.state.vvvv + gpr; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op1Kind = OpKind.Memory; @@ -1327,7 +1327,7 @@ sealed class OpCodeHandler_VEX_Hv_Ev : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -1341,7 +1341,7 @@ sealed class OpCodeHandler_VEX_Hv_Ev : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op1Kind = OpKind.Memory; @@ -1361,7 +1361,7 @@ sealed class OpCodeHandler_VEX_Hv_Ed_Id : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; @@ -1376,7 +1376,7 @@ sealed class OpCodeHandler_VEX_Hv_Ed_Id : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + Register.EAX; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + Register.EAX; } else { instruction.Op1Kind = OpKind.Memory; @@ -1403,7 +1403,7 @@ sealed class OpCodeHandler_VEX_GvM_VX_Ib : OpCodeHandlerModRM { if ((decoder.state.vvvv_invalidCheck & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -1414,7 +1414,7 @@ sealed class OpCodeHandler_VEX_GvM_VX_Ib : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op0Kind = OpKind.Memory; @@ -1422,7 +1422,7 @@ sealed class OpCodeHandler_VEX_GvM_VX_Ib : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + baseReg; + instruction.Op1Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + baseReg; instruction.Op2Kind = OpKind.Immediate8; instruction.InternalImmediate8 = decoder.ReadByte(); } @@ -1442,7 +1442,7 @@ sealed class OpCodeHandler_VEX_Gv_Ev_Ib : OpCodeHandlerModRM { if ((decoder.state.vvvv_invalidCheck & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -1452,11 +1452,11 @@ sealed class OpCodeHandler_VEX_Gv_Ev_Ib : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + gpr; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op1Kind = OpKind.Memory; @@ -1481,7 +1481,7 @@ sealed class OpCodeHandler_VEX_Gv_Ev_Id : OpCodeHandlerModRM { if ((decoder.state.vvvv_invalidCheck & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -1491,11 +1491,11 @@ sealed class OpCodeHandler_VEX_Gv_Ev_Id : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + gpr; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op1Kind = OpKind.Memory; @@ -1513,7 +1513,7 @@ sealed class OpCodeHandler_VEX_VT_SIBMEM : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - if (((decoder.state.vvvv_invalidCheck | decoder.state.extraRegisterBase) & decoder.invalidCheckMask) != 0) + if (((decoder.state.vvvv_invalidCheck | decoder.state.zs.extraRegisterBase) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -1535,7 +1535,7 @@ sealed class OpCodeHandler_VEX_SIBMEM_VT : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - if (((decoder.state.vvvv_invalidCheck | decoder.state.extraRegisterBase) & decoder.invalidCheckMask) != 0) + if (((decoder.state.vvvv_invalidCheck | decoder.state.zs.extraRegisterBase) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -1557,7 +1557,7 @@ sealed class OpCodeHandler_VEX_VT : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - if (((decoder.state.vvvv_invalidCheck | decoder.state.extraRegisterBase) & decoder.invalidCheckMask) != 0) + if (((decoder.state.vvvv_invalidCheck | decoder.state.zs.extraRegisterBase) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -1573,7 +1573,7 @@ sealed class OpCodeHandler_VEX_VT_RT_HT : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - if (decoder.invalidCheckMask != 0 && (decoder.state.vvvv > 7 || decoder.state.extraRegisterBase != 0)) + if (decoder.invalidCheckMask != 0 && (decoder.state.vvvv > 7 || decoder.state.zs.extraRegisterBase != 0)) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -1587,7 +1587,7 @@ sealed class OpCodeHandler_VEX_VT_RT_HT : OpCodeHandlerModRM { //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)decoder.state.rm + Register.TMM0; if (decoder.invalidCheckMask != 0) { - if (decoder.state.extraBaseRegisterBase != 0 || decoder.state.reg == decoder.state.vvvv || decoder.state.reg == decoder.state.rm || decoder.state.rm == decoder.state.vvvv) + if (decoder.state.zs.extraBaseRegisterBase != 0 || decoder.state.reg == decoder.state.vvvv || decoder.state.reg == decoder.state.rm || decoder.state.rm == decoder.state.vvvv) decoder.SetInvalidInstruction(); } } @@ -1608,7 +1608,7 @@ sealed class OpCodeHandler_VEX_Gq_HK_RK : OpCodeHandlerModRM { instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + Register.RAX; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + Register.RAX; Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; instruction.Op1Register = (int)(decoder.state.vvvv & 7) + Register.K0; @@ -1633,7 +1633,7 @@ sealed class OpCodeHandler_VEX_VK_R_Ib : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - if (((decoder.state.vvvv_invalidCheck | decoder.state.extraRegisterBase) & decoder.invalidCheckMask) != 0) + if (((decoder.state.vvvv_invalidCheck | decoder.state.zs.extraRegisterBase) & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); instruction.InternalSetCodeNoCheck(code); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -1642,7 +1642,7 @@ sealed class OpCodeHandler_VEX_VK_R_Ib : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else decoder.SetInvalidInstruction(); @@ -1658,7 +1658,7 @@ sealed class OpCodeHandler_VEX_K_Jb : OpCodeHandlerModRM { public override void Decode(Decoder decoder, ref Instruction instruction) { Debug.Assert(decoder.state.Encoding == EncodingKind.VEX || decoder.state.Encoding == EncodingKind.XOP); - decoder.state.flags |= StateFlags.BranchImm8; + decoder.state.zs.flags |= StateFlags.BranchImm8; if (decoder.invalidCheckMask != 0 && decoder.state.vvvv > 7) decoder.SetInvalidInstruction(); Static.Assert(OpKind.Register == 0 ? 0 : -1); @@ -1707,7 +1707,7 @@ sealed class OpCodeHandler_VEX_Gv_Ev : OpCodeHandlerModRM { if ((decoder.state.vvvv_invalidCheck & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -1717,11 +1717,11 @@ sealed class OpCodeHandler_VEX_Gv_Ev : OpCodeHandlerModRM { } Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.reg + decoder.state.extraRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.reg + decoder.state.zs.extraRegisterBase) + gpr; if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op1Kind = OpKind.Register; - instruction.Op1Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op1Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op1Kind = OpKind.Memory; @@ -1744,7 +1744,7 @@ sealed class OpCodeHandler_VEX_Ev : OpCodeHandlerModRM { if ((decoder.state.vvvv_invalidCheck & decoder.invalidCheckMask) != 0) decoder.SetInvalidInstruction(); Register gpr; - if (((uint)decoder.state.flags & decoder.is64bMode_and_W) != 0) { + if (((uint)decoder.state.zs.flags & decoder.is64bMode_and_W) != 0) { instruction.InternalSetCodeNoCheck(code64); gpr = Register.RAX; } @@ -1755,7 +1755,7 @@ sealed class OpCodeHandler_VEX_Ev : OpCodeHandlerModRM { if (decoder.state.mod == 3) { Static.Assert(OpKind.Register == 0 ? 0 : -1); //instruction.Op0Kind = OpKind.Register; - instruction.Op0Register = (int)(decoder.state.rm + decoder.state.extraBaseRegisterBase) + gpr; + instruction.Op0Register = (int)(decoder.state.rm + decoder.state.zs.extraBaseRegisterBase) + gpr; } else { instruction.Op0Kind = OpKind.Memory; From 1503a5ad25ab4bbf4a766b026faeef27b22cb635 Mon Sep 17 00:00:00 2001 From: wtfsck Date: Sat, 12 Feb 2022 18:23:14 +0100 Subject: [PATCH 5/6] Shift first --- src/csharp/Intel/Iced/Intel/Decoder.cs | 6 +++--- .../Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/csharp/Intel/Iced/Intel/Decoder.cs b/src/csharp/Intel/Iced/Intel/Decoder.cs index 8229a4183..cd93848c6 100644 --- a/src/csharp/Intel/Iced/Intel/Decoder.cs +++ b/src/csharp/Intel/Iced/Intel/Decoder.cs @@ -344,9 +344,9 @@ internal struct State { state.operandSize = OpSize.Size64; } state.zs.flags = flags2; - state.zs.extraRegisterBase = (b & 4) << 1; - state.zs.extraIndexRegisterBase = (b & 2) << 2; - state.zs.extraBaseRegisterBase = (b & 1) << 3; + state.zs.extraRegisterBase = (b << 1) & 8; + state.zs.extraIndexRegisterBase = (b << 2) & 8; + state.zs.extraBaseRegisterBase = (b << 3) & 8; b = ReadByte(); } diff --git a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs index cd218ab84..c5018f3e1 100644 --- a/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs +++ b/src/csharp/Intel/Iced/Intel/DecoderInternal/OpCodeHandlers_Legacy.cs @@ -211,9 +211,9 @@ sealed class OpCodeHandler_PrefixREX : OpCodeHandler { else decoder.state.operandSize = OpSize.Size16; } - decoder.state.zs.extraRegisterBase = (rex & 4) << 1; - decoder.state.zs.extraIndexRegisterBase = (rex & 2) << 2; - decoder.state.zs.extraBaseRegisterBase = (rex & 1) << 3; + decoder.state.zs.extraRegisterBase = (rex << 1) & 8; + decoder.state.zs.extraIndexRegisterBase = (rex << 2) & 8; + decoder.state.zs.extraBaseRegisterBase = (rex << 3) & 8; decoder.CallOpCodeHandlerXXTable(ref instruction); } From 51612094e42647358fb0762ead2ae87cfaf704f7 Mon Sep 17 00:00:00 2001 From: wtfsck Date: Sat, 12 Feb 2022 18:23:19 +0100 Subject: [PATCH 6/6] Use the local not the field --- src/csharp/Intel/Iced/Intel/Decoder.cs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/csharp/Intel/Iced/Intel/Decoder.cs b/src/csharp/Intel/Iced/Intel/Decoder.cs index cd93848c6..e1f4688c9 100644 --- a/src/csharp/Intel/Iced/Intel/Decoder.cs +++ b/src/csharp/Intel/Iced/Intel/Decoder.cs @@ -368,11 +368,11 @@ internal struct State { // RIP rel ops are common, but invalid/lock bits are usually never set, so exit early if possible if ((flags & (StateFlags.IsInvalid | StateFlags.Lock | StateFlags.IpRel64)) == StateFlags.IpRel64) return; - if ((state.zs.flags & StateFlags.IpRel64) == 0) { + if ((flags & StateFlags.IpRel64) == 0) { // Undo what we did above instruction.MemoryDisplacement64 = addr - ip; } - if ((state.zs.flags & StateFlags.IpRel32) != 0) + if ((flags & StateFlags.IpRel32) != 0) instruction.MemoryDisplacement64 = (uint)instruction.MemoryDisplacement64 + (uint)ip; if ((flags & StateFlags.IsInvalid) != 0 ||