Differences with Nuked-OPM

[jotego]

A quick check has revealed some differences between your code and Nuked's. For instance:

https://github.com/ika-musume/IKAOPM/blob/7cea2dfc242154f9aff333180f29f4a854454e76/HDL/IKAOPM_modules/IKAOPM_noise.v#L64C58-L64C69

And

https://github.com/nukeykt/Nuked-OPM/blob/a0ab44be60cb28b68431779829454ddf3284f272/opm.c#L1265

where he is comparing the LFSR with all 1's and you are comparing with all 0's. His implementation is also based on a die shot so I don't know which one is the right one. I'm opening up the issue here, as I have talked with you more recently.

I think there are other small differences in how the noise is generated between the two of you.

[ika-musume]

I double-checked the noise block in the die shot, and I was not able to found any problems with my schematics yet.

First, let's look at the LSFR's initialization circuits. Note that GLOBAL.MRST is a positive logic signal, which becomes 1 on reset. This causes the output of AOI21, highlighted in magenta, to be 1. I took the "reset value" to be 0. If the LFSR contains binary 1111... at reset, this would be negative logic.

Evey dynamic shift register bits of the LFSR have complementary outputs. Q passes the value to the next register, and /Q connects to a 17-input NOR(wired-OR+INV in the photo). Since the input was negative logic, Q is also negative logic, and /Q is positive logic. Since the NOTP inverts Q of MCYC0 DFF, Q of MCYC1 DFF and MCYC2 DFF is positive logic.

Anyway, they are all positive logic, and they connected to a 17-input NOR. Here they mean noise_lfsr[15:0] and xor_flag in my code. This can be considered a zero detector with the positive logic output, since the output will be 1 only if all inputs are 0.

When the output of the 17-input NOR becomes 1, the output of NOR2 becomes 0.

Let's look at the first picture again. The output of NOR2 is connected to the NOR3. In normal operation, MRST = 0, and the value of MCYC17-00 DFF is 1 during the LFSR value update period. Then all inputs of the NOR3 will be 0, and the output will be 1.

If the output of the NOR3 is 1, the output of the AOI21 will be 0. I assumed in the first paragraph that the polarity of the LFSR's input is negative logic, so we can think of the LFSR as having a input value 1.

IKAOPM/HDL/IKAOPM_modules/IKAOPM_noise.v

Line 64 in 7cea2df

wire xor_fdbk = (xor_flag ^ noise_lfsr[2]) | (noise_lfsr == 16'h0000 && xor_flag == 1'b0);

I haven't read nukeykt's code. He might have written his code with the output of the taps in the LFSR as negative logic.

[ika-musume]

In the register-to-register connections of all YM2XXX FM chips, the polarity of the data changes every time it passes through a single DFF+comb logic. Very confusing and annoying. Many nets of the schematics are annotated with positive and negative logic.

[jotego]

You can use ~{name} to add a bar on top of a singal name on KiCAD, so it will be clear whether the logic is active high or low. It is also customary to add some sort of suffix to verilog signals such as _n or _b to mark active low signals. That would make things clearer.

I will review Nuked's code after your comments above

[ika-musume]

Yesterday, when I replied, it was over 2 am in my local time. I took another look at the die shot during the day today and didn't find anything that contradicts what I said yesterday. I'll keep the issue open anyway.

[ika-musume]

I reviewed the nukeykt's code, and the behavior of his C code and my Verilog code is exactly the same, except that he implemented all the circuits "as is", and I implemented them with some polarity changes. They are simply differences in intermediate data polarity. I will close the case.

[jotego]

Thank you