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Tools for emulating transistor-level netlists on FPGAs http://fpga-netlist-tools.github.com
Synchronize the input signals to avoid metastability issues that cause incorrect data bus reads in a 1541 within a few milliseconds after reset.
Latest commit 243e49f
Apr 11, 2011
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Tools for translating transistor netlists to HDL in a style that supports switch-level emulation. To run the apple1basic demo, install verilator and then do a "make demo". The verilator translation and C++ compile will take several minutes, and the apple1basic code, the statement "PRINT 1234/7", will take an additional several minutes before the response is given on the console. See verilator/sim_main.cpp for the simulation code. The 6502 model itself is in verilog/chip_6502.v.