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Tools for emulating transistor-level netlists on FPGAs
JavaScript Verilog Python Assembly Objective-C C++
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Ingo Korb
Ingo Korb Add synchronizers on all input lines for godil6502 target
Synchronize the input signals to avoid metastability issues that cause
incorrect data bus reads in a 1541 within a few milliseconds after reset.
Latest commit 243e49f Apr 11, 2011
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6502-test-code fix the keyboard I/O problem Jan 13, 2011
iverilog add in the 4004 Verilog simulation environment Mar 30, 2011
masks much better SVG polygons from the 400x bitmaps Apr 2, 2011
netlist-translation added magic technology file to correctly extract 4004; progress on Ve… Mar 25, 2011
support much better SVG polygons from the 400x bitmaps Apr 2, 2011
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verilator add some .gitignore files to reduce git chatter Jan 15, 2011
verilog some progress toward 4004 Verilog simulation---control flow instructi… Mar 30, 2011
visual6502 update the nodenames.js and transdefs.js from visual6502---contains s… Feb 16, 2011
.gitignore add some .gitignore files to reduce git chatter Jan 15, 2011
LICENSE add a LICENSE file; break out ROM into rom.v Jan 15, 2011
Makefile add a README file and copyright notices Dec 18, 2010
README

README

Tools for translating transistor netlists to HDL in a style that
supports switch-level emulation.

To run the apple1basic demo, install verilator and then do a "make
demo".  The verilator translation and C++ compile will take several
minutes, and the apple1basic code, the statement "PRINT 1234/7", will
take an additional several minutes before the response is given on the
console.

See verilator/sim_main.cpp for the simulation code.  The 6502 model
itself is in verilog/chip_6502.v.
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