add in the 4004 Verilog simulation environment

ikorb · Mar 30, 2011 · 3a41ec6 · 3a41ec6
1 parent c65dd8f
commit 3a41ec6
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diff --git a/iverilog/4004/Makefile b/iverilog/4004/Makefile
@@ -0,0 +1,9 @@
+VSRC = ../../verilog/{test_4004.v,chip_4004.v,clocks_4004.v,models.v,rom_4004.v}
+VFLAGS = -Wall
+
+test:
+	iverilog $(VFLAGS) -DW=6 -DMAXTICKS=10000000 -DQUARTERCYCLE=250 -I../../verilog $(VSRC)
+	./a.out -lxt2
+
+clean:
+	rm -f a.out *.lxt
diff --git a/iverilog/4004/test1.asm b/iverilog/4004/test1.asm
@@ -0,0 +1,5 @@
+      ldm 3
+      xch 2
+      ldm 9
+loop: add 2
+      jun loop
diff --git a/iverilog/4004/test1.lst b/iverilog/4004/test1.lst
@@ -0,0 +1,5 @@
+D3                ldm 3
+B2                xch 2
+D9                ldm 9
+82          loop: add 2
+40 03             jun loop