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trap.c
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/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* or http://www.opensolaris.org/os/licensing.
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
*/
/* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
/* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */
/* All Rights Reserved */
/* */
/* Copyright (c) 1987, 1988 Microsoft Corporation */
/* All Rights Reserved */
/* */
/*
* Copyright 2018 Joyent, Inc.
*/
#include <sys/types.h>
#include <sys/sysmacros.h>
#include <sys/param.h>
#include <sys/signal.h>
#include <sys/systm.h>
#include <sys/user.h>
#include <sys/proc.h>
#include <sys/disp.h>
#include <sys/class.h>
#include <sys/core.h>
#include <sys/syscall.h>
#include <sys/cpuvar.h>
#include <sys/vm.h>
#include <sys/sysinfo.h>
#include <sys/fault.h>
#include <sys/stack.h>
#include <sys/psw.h>
#include <sys/regset.h>
#include <sys/fp.h>
#include <sys/trap.h>
#include <sys/kmem.h>
#include <sys/vtrace.h>
#include <sys/cmn_err.h>
#include <sys/prsystm.h>
#include <sys/mutex_impl.h>
#include <sys/machsystm.h>
#include <sys/archsystm.h>
#include <sys/sdt.h>
#include <sys/avintr.h>
#include <sys/kobj.h>
#include <vm/hat.h>
#include <vm/seg_kmem.h>
#include <vm/as.h>
#include <vm/seg.h>
#include <vm/hat_pte.h>
#include <vm/hat_i86.h>
#include <sys/procfs.h>
#include <sys/reboot.h>
#include <sys/debug.h>
#include <sys/debugreg.h>
#include <sys/modctl.h>
#include <sys/aio_impl.h>
#include <sys/tnf.h>
#include <sys/tnf_probe.h>
#include <sys/cred.h>
#include <sys/mman.h>
#include <sys/x86_archext.h>
#include <sys/copyops.h>
#include <c2/audit.h>
#include <sys/ftrace.h>
#include <sys/panic.h>
#include <sys/traptrace.h>
#include <sys/ontrap.h>
#include <sys/cpc_impl.h>
#include <sys/bootconf.h>
#include <sys/bootinfo.h>
#include <sys/promif.h>
#include <sys/mach_mmu.h>
#if defined(__xpv)
#include <sys/hypervisor.h>
#endif
#include <sys/contract/process_impl.h>
#define USER 0x10000 /* user-mode flag added to trap type */
static const char *trap_type_mnemonic[] = {
"de", "db", "2", "bp",
"of", "br", "ud", "nm",
"df", "9", "ts", "np",
"ss", "gp", "pf", "15",
"mf", "ac", "mc", "xf"
};
static const char *trap_type[] = {
"Divide error", /* trap id 0 */
"Debug", /* trap id 1 */
"NMI interrupt", /* trap id 2 */
"Breakpoint", /* trap id 3 */
"Overflow", /* trap id 4 */
"BOUND range exceeded", /* trap id 5 */
"Invalid opcode", /* trap id 6 */
"Device not available", /* trap id 7 */
"Double fault", /* trap id 8 */
"Coprocessor segment overrun", /* trap id 9 */
"Invalid TSS", /* trap id 10 */
"Segment not present", /* trap id 11 */
"Stack segment fault", /* trap id 12 */
"General protection", /* trap id 13 */
"Page fault", /* trap id 14 */
"Reserved", /* trap id 15 */
"x87 floating point error", /* trap id 16 */
"Alignment check", /* trap id 17 */
"Machine check", /* trap id 18 */
"SIMD floating point exception", /* trap id 19 */
};
#define TRAP_TYPES (sizeof (trap_type) / sizeof (trap_type[0]))
#define SLOW_SCALL_SIZE 2
#define FAST_SCALL_SIZE 2
int tudebug = 0;
int tudebugbpt = 0;
int tudebugfpe = 0;
int tudebugsse = 0;
#if defined(TRAPDEBUG) || defined(lint)
int tdebug = 0;
int lodebug = 0;
int faultdebug = 0;
#else
#define tdebug 0
#define lodebug 0
#define faultdebug 0
#endif /* defined(TRAPDEBUG) || defined(lint) */
#if defined(TRAPTRACE)
/*
* trap trace record for cpu0 is allocated here.
* trap trace records for non-boot cpus are allocated in mp_startup_init().
*/
static trap_trace_rec_t trap_tr0[TRAPTR_NENT];
trap_trace_ctl_t trap_trace_ctl[NCPU] = {
{
(uintptr_t)trap_tr0, /* next record */
(uintptr_t)trap_tr0, /* first record */
(uintptr_t)(trap_tr0 + TRAPTR_NENT), /* limit */
(uintptr_t)0 /* current */
},
};
/*
* default trap buffer size
*/
size_t trap_trace_bufsize = TRAPTR_NENT * sizeof (trap_trace_rec_t);
int trap_trace_freeze = 0;
int trap_trace_off = 0;
/*
* A dummy TRAPTRACE entry to use after death.
*/
trap_trace_rec_t trap_trace_postmort;
static void dump_ttrace(void);
#endif /* TRAPTRACE */
static void dumpregs(struct regs *);
static void showregs(uint_t, struct regs *, caddr_t);
static int kern_gpfault(struct regs *);
/*ARGSUSED*/
static int
die(uint_t type, struct regs *rp, caddr_t addr, processorid_t cpuid)
{
struct panic_trap_info ti;
const char *trap_name, *trap_mnemonic;
if (type < TRAP_TYPES) {
trap_name = trap_type[type];
trap_mnemonic = trap_type_mnemonic[type];
} else {
trap_name = "trap";
trap_mnemonic = "-";
}
#ifdef TRAPTRACE
TRAPTRACE_FREEZE;
#endif
ti.trap_regs = rp;
ti.trap_type = type & ~USER;
ti.trap_addr = addr;
curthread->t_panic_trap = &ti;
if (type == T_PGFLT && addr < (caddr_t)kernelbase) {
panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p "
"occurred in module \"%s\" due to %s",
type, trap_mnemonic, trap_name, (void *)rp, (void *)addr,
mod_containing_pc((caddr_t)rp->r_pc),
addr < (caddr_t)PAGESIZE ?
"a NULL pointer dereference" :
"an illegal access to a user address");
} else
panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p",
type, trap_mnemonic, trap_name, (void *)rp, (void *)addr);
return (0);
}
/*
* Rewrite the instruction at pc to be an int $T_SYSCALLINT instruction.
*
* int <vector> is two bytes: 0xCD <vector>
*/
static int
rewrite_syscall(caddr_t pc)
{
uchar_t instr[SLOW_SCALL_SIZE] = { 0xCD, T_SYSCALLINT };
if (uwrite(curthread->t_procp, instr, SLOW_SCALL_SIZE,
(uintptr_t)pc) != 0)
return (1);
return (0);
}
/*
* Test to see if the instruction at pc is sysenter or syscall. The second
* argument should be the x86 feature flag corresponding to the expected
* instruction.
*
* sysenter is two bytes: 0x0F 0x34
* syscall is two bytes: 0x0F 0x05
* int $T_SYSCALLINT is two bytes: 0xCD 0x91
*/
static int
instr_is_other_syscall(caddr_t pc, int which)
{
uchar_t instr[FAST_SCALL_SIZE];
ASSERT(which == X86FSET_SEP || which == X86FSET_ASYSC || which == 0xCD);
if (copyin_nowatch(pc, (caddr_t)instr, FAST_SCALL_SIZE) != 0)
return (0);
switch (which) {
case X86FSET_SEP:
if (instr[0] == 0x0F && instr[1] == 0x34)
return (1);
break;
case X86FSET_ASYSC:
if (instr[0] == 0x0F && instr[1] == 0x05)
return (1);
break;
case 0xCD:
if (instr[0] == 0xCD && instr[1] == T_SYSCALLINT)
return (1);
break;
}
return (0);
}
static const char *
syscall_insn_string(int syscall_insn)
{
switch (syscall_insn) {
case X86FSET_SEP:
return ("sysenter");
case X86FSET_ASYSC:
return ("syscall");
case 0xCD:
return ("int");
default:
return ("Unknown");
}
}
static int
ldt_rewrite_syscall(struct regs *rp, proc_t *p, int syscall_insn)
{
caddr_t linearpc;
int return_code = 0;
mutex_enter(&p->p_ldtlock); /* Must be held across linear_pc() */
if (linear_pc(rp, p, &linearpc) == 0) {
/*
* If another thread beat us here, it already changed
* this site to the slower (int) syscall instruction.
*/
if (instr_is_other_syscall(linearpc, 0xCD)) {
return_code = 1;
} else if (instr_is_other_syscall(linearpc, syscall_insn)) {
if (rewrite_syscall(linearpc) == 0) {
return_code = 1;
}
#ifdef DEBUG
else
cmn_err(CE_WARN, "failed to rewrite %s "
"instruction in process %d",
syscall_insn_string(syscall_insn),
p->p_pid);
#endif /* DEBUG */
}
}
mutex_exit(&p->p_ldtlock); /* Must be held across linear_pc() */
return (return_code);
}
/*
* Test to see if the instruction at pc is a system call instruction.
*
* The bytes of an lcall instruction used for the syscall trap.
* static uchar_t lcall[7] = { 0x9a, 0, 0, 0, 0, 0x7, 0 };
* static uchar_t lcallalt[7] = { 0x9a, 0, 0, 0, 0, 0x27, 0 };
*/
#define LCALLSIZE 7
static int
instr_is_lcall_syscall(caddr_t pc)
{
uchar_t instr[LCALLSIZE];
if (copyin_nowatch(pc, (caddr_t)instr, LCALLSIZE) == 0 &&
instr[0] == 0x9a &&
instr[1] == 0 &&
instr[2] == 0 &&
instr[3] == 0 &&
instr[4] == 0 &&
(instr[5] == 0x7 || instr[5] == 0x27) &&
instr[6] == 0)
return (1);
return (0);
}
#ifdef __amd64
/*
* In the first revisions of amd64 CPUs produced by AMD, the LAHF and
* SAHF instructions were not implemented in 64-bit mode. Later revisions
* did implement these instructions. An extension to the cpuid instruction
* was added to check for the capability of executing these instructions
* in 64-bit mode.
*
* Intel originally did not implement these instructions in EM64T either,
* but added them in later revisions.
*
* So, there are different chip revisions by both vendors out there that
* may or may not implement these instructions. The easy solution is to
* just always emulate these instructions on demand.
*
* SAHF == store %ah in the lower 8 bits of %rflags (opcode 0x9e)
* LAHF == load the lower 8 bits of %rflags into %ah (opcode 0x9f)
*/
#define LSAHFSIZE 1
static int
instr_is_lsahf(caddr_t pc, uchar_t *instr)
{
if (copyin_nowatch(pc, (caddr_t)instr, LSAHFSIZE) == 0 &&
(*instr == 0x9e || *instr == 0x9f))
return (1);
return (0);
}
/*
* Emulate the LAHF and SAHF instructions. The reference manuals define
* these instructions to always load/store bit 1 as a 1, and bits 3 and 5
* as a 0. The other, defined, bits are copied (the PS_ICC bits and PS_P).
*
* Note that %ah is bits 8-15 of %rax.
*/
static void
emulate_lsahf(struct regs *rp, uchar_t instr)
{
if (instr == 0x9e) {
/* sahf. Copy bits from %ah to flags. */
rp->r_ps = (rp->r_ps & ~0xff) |
((rp->r_rax >> 8) & PSL_LSAHFMASK) | PS_MB1;
} else {
/* lahf. Copy bits from flags to %ah. */
rp->r_rax = (rp->r_rax & ~0xff00) |
(((rp->r_ps & PSL_LSAHFMASK) | PS_MB1) << 8);
}
rp->r_pc += LSAHFSIZE;
}
#endif /* __amd64 */
#ifdef OPTERON_ERRATUM_91
/*
* Test to see if the instruction at pc is a prefetch instruction.
*
* The first byte of prefetch instructions is always 0x0F.
* The second byte is 0x18 for regular prefetch or 0x0D for AMD 3dnow prefetch.
* The third byte (ModRM) contains the register field bits (bits 3-5).
* These bits must be between 0 and 3 inclusive for regular prefetch and
* 0 and 1 inclusive for AMD 3dnow prefetch.
*
* In 64-bit mode, there may be a one-byte REX prefex (0x40-0x4F).
*/
static int
cmp_to_prefetch(uchar_t *p)
{
#ifdef _LP64
if ((p[0] & 0xF0) == 0x40) /* 64-bit REX prefix */
p++;
#endif
return ((p[0] == 0x0F && p[1] == 0x18 && ((p[2] >> 3) & 7) <= 3) ||
(p[0] == 0x0F && p[1] == 0x0D && ((p[2] >> 3) & 7) <= 1));
}
static int
instr_is_prefetch(caddr_t pc)
{
uchar_t instr[4]; /* optional REX prefix plus 3-byte opcode */
return (copyin_nowatch(pc, instr, sizeof (instr)) == 0 &&
cmp_to_prefetch(instr));
}
#endif /* OPTERON_ERRATUM_91 */
/*
* Called from the trap handler when a processor trap occurs.
*
* Note: All user-level traps that might call stop() must exit
* trap() by 'goto out' or by falling through.
* Note Also: trap() is usually called with interrupts enabled, (PS_IE == 1)
* however, there are paths that arrive here with PS_IE == 0 so special care
* must be taken in those cases.
*/
void
trap(struct regs *rp, caddr_t addr, processorid_t cpuid)
{
kthread_t *ct = curthread;
enum seg_rw rw;
unsigned type;
proc_t *p = ttoproc(ct);
klwp_t *lwp = ttolwp(ct);
uintptr_t lofault;
label_t *onfault;
faultcode_t pagefault(), res, errcode;
enum fault_type fault_type;
k_siginfo_t siginfo;
uint_t fault = 0;
int mstate;
int sicode = 0;
int watchcode;
int watchpage;
caddr_t vaddr;
size_t sz;
int ta;
#ifdef __amd64
uchar_t instr;
#endif
ASSERT_STACK_ALIGNED();
errcode = 0;
mstate = 0;
rw = S_OTHER;
type = rp->r_trapno;
CPU_STATS_ADDQ(CPU, sys, trap, 1);
ASSERT(ct->t_schedflag & TS_DONT_SWAP);
if (type == T_PGFLT) {
errcode = rp->r_err;
if (errcode & PF_ERR_WRITE)
rw = S_WRITE;
else if ((caddr_t)rp->r_pc == addr ||
(mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC)))
rw = S_EXEC;
else
rw = S_READ;
#if defined(__i386)
/*
* Pentium Pro work-around
*/
if ((errcode & PF_ERR_PROT) && pentiumpro_bug4046376) {
uint_t attr;
uint_t priv_violation;
uint_t access_violation;
if (hat_getattr(addr < (caddr_t)kernelbase ?
curproc->p_as->a_hat : kas.a_hat, addr, &attr)
== -1) {
errcode &= ~PF_ERR_PROT;
} else {
priv_violation = (errcode & PF_ERR_USER) &&
!(attr & PROT_USER);
access_violation = (errcode & PF_ERR_WRITE) &&
!(attr & PROT_WRITE);
if (!priv_violation && !access_violation)
goto cleanup;
}
}
#endif /* __i386 */
} else if (type == T_SGLSTP && lwp != NULL)
lwp->lwp_pcb.pcb_drstat = (uintptr_t)addr;
if (tdebug)
showregs(type, rp, addr);
if (USERMODE(rp->r_cs)) {
/*
* Set up the current cred to use during this trap. u_cred
* no longer exists. t_cred is used instead.
* The current process credential applies to the thread for
* the entire trap. If trapping from the kernel, this
* should already be set up.
*/
if (ct->t_cred != p->p_cred) {
cred_t *oldcred = ct->t_cred;
/*
* DTrace accesses t_cred in probe context. t_cred
* must always be either NULL, or point to a valid,
* allocated cred structure.
*/
ct->t_cred = crgetcred();
crfree(oldcred);
}
ASSERT(lwp != NULL);
type |= USER;
ASSERT(lwptoregs(lwp) == rp);
lwp->lwp_state = LWP_SYS;
switch (type) {
case T_PGFLT + USER:
if ((caddr_t)rp->r_pc == addr)
mstate = LMS_TFAULT;
else
mstate = LMS_DFAULT;
break;
default:
mstate = LMS_TRAP;
break;
}
/* Kernel probe */
TNF_PROBE_1(thread_state, "thread", /* CSTYLED */,
tnf_microstate, state, mstate);
mstate = new_mstate(ct, mstate);
bzero(&siginfo, sizeof (siginfo));
}
switch (type) {
case T_PGFLT + USER:
case T_SGLSTP:
case T_SGLSTP + USER:
case T_BPTFLT + USER:
break;
default:
FTRACE_2("trap(): type=0x%lx, regs=0x%lx",
(ulong_t)type, (ulong_t)rp);
break;
}
switch (type) {
case T_SIMDFPE:
/* Make sure we enable interrupts before die()ing */
sti(); /* The SIMD exception comes in via cmninttrap */
/*FALLTHROUGH*/
default:
if (type & USER) {
if (tudebug)
showregs(type, rp, (caddr_t)0);
printf("trap: Unknown trap type %d in user mode\n",
type & ~USER);
siginfo.si_signo = SIGILL;
siginfo.si_code = ILL_ILLTRP;
siginfo.si_addr = (caddr_t)rp->r_pc;
siginfo.si_trapno = type & ~USER;
fault = FLTILL;
} else {
(void) die(type, rp, addr, cpuid);
/*NOTREACHED*/
}
break;
case T_PGFLT: /* system page fault */
/*
* If we're under on_trap() protection (see <sys/ontrap.h>),
* set ot_trap and bounce back to the on_trap() call site
* via the installed trampoline.
*/
if ((ct->t_ontrap != NULL) &&
(ct->t_ontrap->ot_prot & OT_DATA_ACCESS)) {
ct->t_ontrap->ot_trap |= OT_DATA_ACCESS;
rp->r_pc = ct->t_ontrap->ot_trampoline;
goto cleanup;
}
/*
* If we have an Instruction fault in kernel mode, then that
* means we've tried to execute a user page (SMEP) or both of
* PAE and NXE are enabled. In either case, given that it's a
* kernel fault, we should panic immediately and not try to make
* any more forward progress. This indicates a bug in the
* kernel, which if execution continued, could be exploited to
* wreak havoc on the system.
*/
if (errcode & PF_ERR_EXEC) {
(void) die(type, rp, addr, cpuid);
}
/*
* We need to check if SMAP is in play. If SMAP is in play, then
* any access to a user page will show up as a protection
* violation. To see if SMAP is enabled we first check if it's a
* user address and whether we have the feature flag set. If we
* do and the interrupted registers do not allow for user
* accesses (PS_ACHK is not enabled), then we need to die
* immediately.
*/
if (addr < (caddr_t)kernelbase &&
is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE &&
(rp->r_ps & PS_ACHK) == 0) {
(void) die(type, rp, addr, cpuid);
}
/*
* See if we can handle as pagefault. Save lofault and onfault
* across this. Here we assume that an address less than
* KERNELBASE is a user fault. We can do this as copy.s
* routines verify that the starting address is less than
* KERNELBASE before starting and because we know that we
* always have KERNELBASE mapped as invalid to serve as a
* "barrier".
*/
lofault = ct->t_lofault;
onfault = ct->t_onfault;
ct->t_lofault = 0;
mstate = new_mstate(ct, LMS_KFAULT);
if (addr < (caddr_t)kernelbase) {
res = pagefault(addr,
(errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 0);
if (res == FC_NOMAP &&
addr < p->p_usrstack &&
grow(addr))
res = 0;
} else {
res = pagefault(addr,
(errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 1);
}
(void) new_mstate(ct, mstate);
/*
* Restore lofault and onfault. If we resolved the fault, exit.
* If we didn't and lofault wasn't set, die.
*/
ct->t_lofault = lofault;
ct->t_onfault = onfault;
if (res == 0)
goto cleanup;
#if defined(OPTERON_ERRATUM_93) && defined(_LP64)
if (lofault == 0 && opteron_erratum_93) {
/*
* Workaround for Opteron Erratum 93. On return from
* a System Managment Interrupt at a HLT instruction
* the %rip might be truncated to a 32 bit value.
* BIOS is supposed to fix this, but some don't.
* If this occurs we simply restore the high order bits.
* The HLT instruction is 1 byte of 0xf4.
*/
uintptr_t rip = rp->r_pc;
if ((rip & 0xfffffffful) == rip) {
rip |= 0xfffffffful << 32;
if (hat_getpfnum(kas.a_hat, (caddr_t)rip) !=
PFN_INVALID &&
(*(uchar_t *)rip == 0xf4 ||
*(uchar_t *)(rip - 1) == 0xf4)) {
rp->r_pc = rip;
goto cleanup;
}
}
}
#endif /* OPTERON_ERRATUM_93 && _LP64 */
#ifdef OPTERON_ERRATUM_91
if (lofault == 0 && opteron_erratum_91) {
/*
* Workaround for Opteron Erratum 91. Prefetches may
* generate a page fault (they're not supposed to do
* that!). If this occurs we simply return back to the
* instruction.
*/
caddr_t pc = (caddr_t)rp->r_pc;
/*
* If the faulting PC is not mapped, this is a
* legitimate kernel page fault that must result in a
* panic. If the faulting PC is mapped, it could contain
* a prefetch instruction. Check for that here.
*/
if (hat_getpfnum(kas.a_hat, pc) != PFN_INVALID) {
if (cmp_to_prefetch((uchar_t *)pc)) {
#ifdef DEBUG
cmn_err(CE_WARN, "Opteron erratum 91 "
"occurred: kernel prefetch"
" at %p generated a page fault!",
(void *)rp->r_pc);
#endif /* DEBUG */
goto cleanup;
}
}
(void) die(type, rp, addr, cpuid);
}
#endif /* OPTERON_ERRATUM_91 */
if (lofault == 0)
(void) die(type, rp, addr, cpuid);
/*
* Cannot resolve fault. Return to lofault.
*/
if (lodebug) {
showregs(type, rp, addr);
traceregs(rp);
}
if (FC_CODE(res) == FC_OBJERR)
res = FC_ERRNO(res);
else
res = EFAULT;
rp->r_r0 = res;
rp->r_pc = ct->t_lofault;
goto cleanup;
case T_PGFLT + USER: /* user page fault */
if (faultdebug) {
char *fault_str;
switch (rw) {
case S_READ:
fault_str = "read";
break;
case S_WRITE:
fault_str = "write";
break;
case S_EXEC:
fault_str = "exec";
break;
default:
fault_str = "";
break;
}
printf("user %s fault: addr=0x%lx errcode=0x%x\n",
fault_str, (uintptr_t)addr, errcode);
}
#if defined(OPTERON_ERRATUM_100) && defined(_LP64)
/*
* Workaround for AMD erratum 100
*
* A 32-bit process may receive a page fault on a non
* 32-bit address by mistake. The range of the faulting
* address will be
*
* 0xffffffff80000000 .. 0xffffffffffffffff or
* 0x0000000100000000 .. 0x000000017fffffff
*
* The fault is always due to an instruction fetch, however
* the value of r_pc should be correct (in 32 bit range),
* so we ignore the page fault on the bogus address.
*/
if (p->p_model == DATAMODEL_ILP32 &&
(0xffffffff80000000 <= (uintptr_t)addr ||
(0x100000000 <= (uintptr_t)addr &&
(uintptr_t)addr <= 0x17fffffff))) {
if (!opteron_erratum_100)
panic("unexpected erratum #100");
if (rp->r_pc <= 0xffffffff)
goto out;
}
#endif /* OPTERON_ERRATUM_100 && _LP64 */
ASSERT(!(curthread->t_flag & T_WATCHPT));
watchpage = (pr_watch_active(p) && pr_is_watchpage(addr, rw));
#ifdef __i386
/*
* In 32-bit mode, the lcall (system call) instruction fetches
* one word from the stack, at the stack pointer, because of the
* way the call gate is constructed. This is a bogus
* read and should not be counted as a read watchpoint.
* We work around the problem here by testing to see if
* this situation applies and, if so, simply jumping to
* the code in locore.s that fields the system call trap.
* The registers on the stack are already set up properly
* due to the match between the call gate sequence and the
* trap gate sequence. We just have to adjust the pc.
*/
if (watchpage && addr == (caddr_t)rp->r_sp &&
rw == S_READ && instr_is_lcall_syscall((caddr_t)rp->r_pc)) {
extern void watch_syscall(void);
rp->r_pc += LCALLSIZE;
watch_syscall(); /* never returns */
/* NOTREACHED */
}
#endif /* __i386 */
vaddr = addr;
if (!watchpage || (sz = instr_size(rp, &vaddr, rw)) <= 0)
fault_type = (errcode & PF_ERR_PROT)? F_PROT: F_INVAL;
else if ((watchcode = pr_is_watchpoint(&vaddr, &ta,
sz, NULL, rw)) != 0) {
if (ta) {
do_watch_step(vaddr, sz, rw,
watchcode, rp->r_pc);
fault_type = F_INVAL;
} else {
bzero(&siginfo, sizeof (siginfo));
siginfo.si_signo = SIGTRAP;
siginfo.si_code = watchcode;
siginfo.si_addr = vaddr;
siginfo.si_trapafter = 0;
siginfo.si_pc = (caddr_t)rp->r_pc;
fault = FLTWATCH;
break;
}
} else {
/* XXX pr_watch_emul() never succeeds (for now) */
if (rw != S_EXEC && pr_watch_emul(rp, vaddr, rw))
goto out;
do_watch_step(vaddr, sz, rw, 0, 0);
fault_type = F_INVAL;
}
res = pagefault(addr, fault_type, rw, 0);
/*
* If pagefault() succeeded, ok.
* Otherwise attempt to grow the stack.
*/
if (res == 0 ||
(res == FC_NOMAP &&
addr < p->p_usrstack &&
grow(addr))) {
lwp->lwp_lastfault = FLTPAGE;
lwp->lwp_lastfaddr = addr;
if (prismember(&p->p_fltmask, FLTPAGE)) {
bzero(&siginfo, sizeof (siginfo));
siginfo.si_addr = addr;
(void) stop_on_fault(FLTPAGE, &siginfo);
}
goto out;
} else if (res == FC_PROT && addr < p->p_usrstack &&
(mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC))) {
report_stack_exec(p, addr);
}
#ifdef OPTERON_ERRATUM_91
/*
* Workaround for Opteron Erratum 91. Prefetches may generate a
* page fault (they're not supposed to do that!). If this
* occurs we simply return back to the instruction.
*
* We rely on copyin to properly fault in the page with r_pc.
*/
if (opteron_erratum_91 &&
addr != (caddr_t)rp->r_pc &&
instr_is_prefetch((caddr_t)rp->r_pc)) {
#ifdef DEBUG
cmn_err(CE_WARN, "Opteron erratum 91 occurred: "
"prefetch at %p in pid %d generated a trap!",
(void *)rp->r_pc, p->p_pid);
#endif /* DEBUG */
goto out;
}
#endif /* OPTERON_ERRATUM_91 */
if (tudebug)
showregs(type, rp, addr);
/*
* In the case where both pagefault and grow fail,
* set the code to the value provided by pagefault.
* We map all errors returned from pagefault() to SIGSEGV.
*/
bzero(&siginfo, sizeof (siginfo));
siginfo.si_addr = addr;
switch (FC_CODE(res)) {
case FC_HWERR:
case FC_NOSUPPORT:
siginfo.si_signo = SIGBUS;
siginfo.si_code = BUS_ADRERR;
fault = FLTACCESS;
break;
case FC_ALIGN:
siginfo.si_signo = SIGBUS;
siginfo.si_code = BUS_ADRALN;
fault = FLTACCESS;
break;
case FC_OBJERR:
if ((siginfo.si_errno = FC_ERRNO(res)) != EINTR) {
siginfo.si_signo = SIGBUS;
siginfo.si_code = BUS_OBJERR;
fault = FLTACCESS;
}
break;
default: /* FC_NOMAP or FC_PROT */
siginfo.si_signo = SIGSEGV;
siginfo.si_code =
(res == FC_NOMAP)? SEGV_MAPERR : SEGV_ACCERR;
fault = FLTBOUNDS;
break;
}
break;
case T_ILLINST + USER: /* invalid opcode fault */
/*
* If the syscall instruction is disabled due to LDT usage, a
* user program that attempts to execute it will trigger a #ud
* trap. Check for that case here. If this occurs on a CPU which
* doesn't even support syscall, the result of all of this will
* be to emulate that particular instruction.
*/
if (p->p_ldt != NULL &&
ldt_rewrite_syscall(rp, p, X86FSET_ASYSC))
goto out;
#ifdef __amd64
/*
* Emulate the LAHF and SAHF instructions if needed.
* See the instr_is_lsahf function for details.
*/
if (p->p_model == DATAMODEL_LP64 &&
instr_is_lsahf((caddr_t)rp->r_pc, &instr)) {
emulate_lsahf(rp, instr);
goto out;
}
#endif
/*FALLTHROUGH*/
if (tudebug)
showregs(type, rp, (caddr_t)0);
siginfo.si_signo = SIGILL;
siginfo.si_code = ILL_ILLOPC;
siginfo.si_addr = (caddr_t)rp->r_pc;
fault = FLTILL;
break;
case T_ZERODIV + USER: /* integer divide by zero */
if (tudebug && tudebugfpe)
showregs(type, rp, (caddr_t)0);
siginfo.si_signo = SIGFPE;
siginfo.si_code = FPE_INTDIV;
siginfo.si_addr = (caddr_t)rp->r_pc;
fault = FLTIZDIV;
break;
case T_OVFLW + USER: /* integer overflow */
if (tudebug && tudebugfpe)
showregs(type, rp, (caddr_t)0);
siginfo.si_signo = SIGFPE;
siginfo.si_code = FPE_INTOVF;
siginfo.si_addr = (caddr_t)rp->r_pc;
fault = FLTIOVF;
break;
/*
* When using an eager FPU on x86, the #NM trap is no longer meaningful.